Vamshi Kumar Rao Mahendrakar

*** ***** *********, *** **, Bronx, NY 10451 646-***-**** ac4bk7@r.postjobfree.com linkedin.com/in/vamshi-mahendrakar

CAREER PROFILE

SoC / ASIC / Digital Design and Verification

EDUCATION

Columbia University, New York, NY

Master of Science in Electrical Engineering. GPA: 3.3/4.0 Dec. 2017

Relevant Coursework: System on Chip Platforms, Computer Architecture, Formal Verification for HW/SW Systems,

Digital VLSI Circuits, Advanced Analog Integrated Circuits, Communication Circuits, and Analog Systems in VLSI.

SRM University, College of Engineering, Chennai, India

Bachelor of Technology in Electronic and Communication Engineering. GPA: 3.9/4.0 Jun. 2016

Relevant Coursework: Linear Integrated circuits, VLSI Circuits and Design, and Microprocessors & Microcontrollers.

TECHNICAL SKILLS

Software & Scripting Languages: C, C++, Perl, TCL, Makefiles Operating Systems: Windows, Linux

Design Tools: Cadence (Spectre, Virtuoso, Encounter), LTSpice, MATLAB, Proteus, Eagle PCB, LabVIEW, Quartus,

ORCADLITE, Synopsis, Mentor QuestaSim, Cadence Stratus HLS

Hardware Languages: VHDL, Verilog, 8051/85/86 Assembly Language, SystemC, SystemVerilog

Verification Tools and Methodologies: Mentor Questa, Cadence JasperGold, UVM, OVM

PROJECT EXPERIENCE

Columbia University, New York, NY

Accelerator for VGG16 Convolutional Neural Network (CNN) Sep. 2017

Dec.2017

Implemented an activation function of ReLU of VGG16 neural network in SystemC using Method, Thread, CThread.

Realized Device Under Test (DUT) and Test Benches communication with a TLM FIFO to classify the test images.

Designed a component level accelerator which is optimized to implement the layers of one stage of convolution layer

and fully connected layer. It is then combined with other stage accelerators to check CNN functionality on system level.

Implemented the accelerator to do space-time exploration with three designs: high performance, low area and a trade-off

between area and performance.

Regularly optimized three designs at the component level using various directives provided by Cadence Stratus HLS.

Full Proof FPV and Bug Hunting of Rush Hour Game Sep. 2017

Dec.2017

Designed a Formal Property Verification plan with Mentor Questa and Cadence JasperGold by adding SVA cover,

assumptions, and assertions properties to constrain and verify the design specification of popular Rush Hour game.

Debugged the design code by analyzing the counterexample waveforms and reduced the state space complexity.

Assertion Based Verification of a Ring FIFO Sep. 2017 Oct. 2017

Property Check: Verified safety and liveness properties of a FIFO with unequal read and write clocks.

Equivalence Check: Developed a wrapper of two 4 Depth FIFO and verified its equivalence with 8 Depth FIFO and

incorporated the use of cut points in the design.

Developing SPI Master Slave Verification IP Sep. 2017 Oct. 2017

Implemented a UVM verification environment with master, slave, and scoreboard to check for the SPI bus protocol.

Created sequences that can model SPI transaction and SPI test class that starts sequences and verifies functionality.

Dynamic Frequency Scaling Feb. 2017 May. 2017

Designed a Frequency Controller for a system that contains multiple units of independent clocks. Frequency of each

unit is calculated periodically based on the occupancy queues and adjusted respective frequencies for synchronous

operation of the system.

Written code for sampling and control modules, synthesized using Synopsis, verified the functionality using Mentor

QuestaSim, and generated layout using Cadence Encounter.

Microprocessor Core Design [Cadence, IBM 90nm Technology] Sep. 2016

Dec. 2016

Designed transistor level microprocessor which can add, subtract, shift, load and store based on an 8-bit instruction set.

Created DRC and LVS clean layouts for 8-bit ripple carry adder, 8-bit logarithmic shifter, 8-bit SRAM and PLA.

Floating Point Accelerator Sep. 2016

Dec. 2016

Designed and optimized IEEE-754 single precision floating-point accelerator which implements exponential and

sinusoidal functions for a given input using RTL design flow.

Created a generalized Moore style ASM and designed its micro-architecture.

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