NARASIMHA ROHIT PODURI

*** *, *** **, ***** St, New York, NY-10027 ● 669-***-****●ac4b83@r.postjobfree.com●linkedin.com/in/rohit-poduri EDUCATION

Columbia University School of Engineering and Applied Science New York, NY MS in Computer Engineering Dec 2017

Relevant Coursework: Computer Architecture, System on Chip Platforms, Formal Verification of HW & SW systems Operating Systems, Computer Networks, Internet of Things, Machine Learning, Cloud Computing and Big Data University of Delhi Netaji Subhas Institute of Technology New Delhi, India BE in Instrumentation and Control Engineering (Hons) May 2015 Relevant Coursework: Digital logic design, Microprocessors, Computer System Organization, Computer Graphics, Artificial Intelligence, Digital Signal Processing, Control Systems, Power Electronics, Analog Circuits WORK EXPERIENCE

Columbia University New York, NY

Course Assistant CSEE 4140- Networking Laboratory Sept 2017-Dec 2017

• Responsibilities included grading assignments and exams, holding office hours, clearing students’ doubts etc. Teledyne Lecroy Corporation Chestnut Ridge, NY

Digital IC design intern IC Design Group June 2017-August 2017

• Formally verified the digital functionality of a monolithic trigger and timebase IC using the Yosys verification tool

• Analyzed functionality based anomalies in the Verilog design and achieved good coverage results Kritikal Solutions Pvt Ltd. Noida, India

Associate Embedded Engineer Embedded Systems and IoT Practices June 2015- June 2016

• Developed the SW and FW modules of an IoT based energy optimizer system for air conditioning systems

• Designed the prototype of an IoT based shower system that monitors water usage and performs data visualization

• Integrated and tested the FW and HW sub systems of a high efficiency battery charger (90%) for electric vehicles PROJECTS

Neural Network based hardware accelerator Sept 2017 – Nov 2017

• Implemented a ReLU based neural network hardware accelerator for classifying images on SystemC

• Allowed transfer of data between the DUT and testbench using SystemC based standard communication protocols User Level Interrupts based Parallelism Sept 2017 – Dec 2017

• Explored user-level interrupts based threading architectures for improving the efficiency of multicore architectures

• Ran simulations of the architecture on gem5 and Pin for development of the threading libraries Startup-Boosted Multicore Round-Robin Scheduler Oct 2017 – Nov 2017

• Added a new scheduling policy to the Linux kernel to support weighted round robin scheduling Acceleration of Neural Network based IDS using GPUs April 2017 - May 2017

• Implemented a parallel version of the Neural Network based IDS problem on GPUs using CUDA

• Analyzed and compared different optimization methods like tiling, prefetching, global memory coalescing etc. Branch Prediction Simulator Feb 2017 - March 2017

• Implemented a Correlating Branch Prediction Simulator using Intel’s Pin tool

• Ran the simulator on an image resizing program in C++ and analyzed the performance of different branch predictors L1 Cache Simulator Jan 2017 - Feb 2017

• Implemented a fully functional cache simulator with L1 cache, victim cache, strided prefetcher etc.

• Analyzed the cache statistics for different SPEC benchmark traces and suggested optimal caching systems Coverage Closure and Bug Hunt Nov 2016- Dec 2016

• Formally verified a FIFO and ALU based RTL Design using SystemVerilog assert, assume and cover properties Linear Programming Optimization Nov 2013- June 2014

• Developed a Linear Programming solver combining the simplex and dual interior algorithm on C

• Parallelized the problem on GPUs using simple parallel programming techniques on CUDA TECHNICAL SKILLS

Languages- C/C++, Python, VHDL, Verilog, SystemVerilog, SystemC, x86, ARM assembly, HTML Tools/Libraries- CUDA, FreeRTOS, MATLAB, AWS Cloud, Intel Pin, Cadence JasperGold, Mentor Questa Hardware platforms- TI MSP430 series, STM32L0 series, Atmel AVR series, Raspberry Pi, Arduino

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