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Electrical Engineering Design

Location:
Fairlawn, Ohio, United States
Salary:
$60,000
Posted:
April 27, 2018

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Resume:

Mohammadreza Asgari

**** *********** **.

Fairlawn, OH 44333 – 4142

Email: ac49tm@r.postjobfree.com Phone: +1-330-***-**** SUMMARY

Analog/mixed-signal IC (design and layout), 6+ years: Data converters (SAR, Sigma-Delta, Extended-Counting ADC), bandgap, LDO, oscillator, VGA, switch-capacitor circuits, very low-noise Opamps, fully-differential/single-ended OTAs, high-speed S/H, SPI interface.

Interface circuits (design and layout), 4 years: Capacitor touch sensor readout circuit, ISFET pH sensor, CMOS based electrical-conductivity sensor, temperature sensor.

Hardware design (simulation, schematic and layout), 4 years: Board-level design for ASICs using Eagle CAD 7.5 plus LTspice and Pspice simulation, schematic and layout design by creating new elements or using standard library.

WORK EXPERIENCE

- Research Assistant – The University of Akron – Akron, OH Aug. 2013- present:

SAR ADC: A 10-bit 5MS/s, INL & DNL < 0.5 LSB, 150 uW, SNR 61dB, ENOB 9.7 Bit, 0.08 mm2, fully- differential SAR ADC, (AMS 5V-180nm CMOS technology)

16-bit Extended-counting ADC: A 16-bit 3MS/s, 1.25V full-range, 1mW, 0.28 mm2, calibration-free EC ADC (6-bit sigma delta_10-bit SAR) (5V-180nm CMOS technology)

10-bit Extended-counting ADC: A 10-bit 3MS/s, 0.14 mm2 (6-bit sigma delta- 4-bit Time mode) (AMS 5V-180nm CMOS technology)

Oscillator: A micro-power fully differential Wien-bridge oscillator with variable capacitor network operating at 10KHz to 100KHz range (0.26 mm2 in AMS 180nm CMOS technology)

IA: A VGA (G=10, 100) bandpass (5K-200KHz) low-noise voltage-mode instrumentation amplifier (Plus analog buffer at the input: 0.132 mm2 in AMS 180nm CMOS technology)

LDO and Bandgap: current and voltage TC < 500ppm/ C, current process sensitivity < 7.5%, LDO’s output process sensitivity < 2% (0.057 mm2 in AMS 5V-180nm CMOS technology)

Touch sensor: capacitor touch sensor readout circuit capable of detecting 5pF to 50pF touch panel capacitance (TSMC 350nm CMOS technology)

ISFET sensor: 2 fabricated ICs (AMS 180nm CMOS technology) 1) A low-noise ISFET chopper amplifier with 950nW power consumption 2) Highly linear ISFET pH sensor with a chemical sensitivity of -37mV/pH in pH range of 3 to 9. 3) A very compact “opamp-less” CVCC ISFET pixel

CMOS-based electrical-conductivity sensor: 4 electrodes were implemented “on-chip” using standard unmodified CMOS technology and the system includes oscillator and two IAs which works in frequency range of 10KHz to 100KHz, fabricated in AMS 1.8V-180nm CMOS technology

Standard analog circuits: Single-ended and fully-differential OTAs/Op-amps with switch-capacitor common-mode feedback, continues/clocked comparators (5V and 1.8V-180nm/ 350 nm CMOS technology)

Clock generator/ SPI interface/ level-shifters/ analog-digital buffers: designed as part of the ADCs

Tapeout: 3

- Research Assistant – Shahid Beheshti University – Sept. 2007- Jan. 2010:

A 132MS/s time-interleaved sigma-delta modulator achieves 80dB SNR, 12-bit ENOB, 10 mW for communication applications (TSMC180nm CMOS technology)

A 500MS/s 60.2dB SNR 74dB SFDR open-loop track-and-hold circuit (TSMC180nm CMOS technology)

A 100MS/s flipped-around sample-and-hold circuit using improved bootstrap switch achieves 68dB SNR and 75dB THD at 10MHz input frequency (TSMC180nm CMOS technology) SKILLS

- PCB design: Simulation of design using Analog Devices amplifier models available in LTspice before design of PCB, schematic and layout verification with Eagle CAD 7.5.

- MATLAB/Simulink (system-level design, behavioral model, and analysis of non-idealities of a circuit specially sigma-delta converter and standard analog blocks)

- Analog environment in Cadence (6 years), SPICE, HSPICE, Spectre, system level design, sub-threshold design, Mixed-signal design, full-chip design, noise/ temperature/ stability/ corner/ process/ reliability analysis

- Layout of full-chip, parasitic extraction (QRC), floor-plan of mixed-signal and switch-capacitor circuits, layout of analog noise sensitive device, layout of pixels, matching, Assura, Debugging DRC/LVS/antenna/density errors

- Verilog/Verilog-AMS (Modeling (sensors/ basic analog circuits/ PLL blocks) using Verilog-AMS embedded in Cadence)

- Experience designing Verilog RTL for mixed-signal SoC (Design Compiler, RTL encounter)

- Test and measurement (DAQ, SignalExpress, LabVIEW, probe-station testing, PCB testing boards)

- C ++ (one year) microcontroller- based projects using C ++

- Biosensors and interfaces implemented with standard CMOS technology, ISFET and conductivity sensor design, coating and encapsulation of ISFET pH sensors

- Design and layout verification in TSMC 350nm, TSMC 180nm, AMS 1.8V-180nm, AMS 5V-180nm CMOS technologies

CERTIFICATE AND WORKSHOPS

Attended the NSF Innovation Corps (I-Corps) program as entrepreneurial lead. July Sept. 2014 EDUCATION

PhD in Electrical Engineering, Analog/Mixed-signal IC design The University of Akron GPA: 3.77 Akron, OH Aug. 2013-present MS in Electrical Engineering, Analog/Mixed-signal IC design Shahid Beheshti University GPA: 3.50 Tehran, Iran Sept. 2007- Jan. 2010 BS in Electrical Engineering

Sadjad University Mashhad, Iran Sept. 2002- Jan. 2007



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