Resume

Sign in

Passionate and self-motivated Electrical Engineering professional.

Location:
Buffalo, New York, United States
Posted:
April 25, 2018

Contact this candidate

Resume:

KAUSHIK SHAHAPURKAR

ac483j@r.postjobfree.com, 253-***-****, www.linkedin.com/in/kaushik-shahapurkar

**** *********** ***, ***.***, Buffalo, NY 14221

SUMMARY

Passionate and self-motivated Electrical Engineering professional with a focus in analog/mixed signal circuit design. Highly skilled in ASIC/VLSI design and proficient in schematic and layout extractions, simulations, DRC check using EDA tools.

EDUCATION

University at Buffalo, The State University of New York, Master of Science, Electrical Engineering (GPA: 3.77/4.0) Dec 2017 Jawaharlal Nehru Technological University, Bachelor’s in Electrical and Electronics Engineering (GPA: 4.0/4.0) June 2016

WORK EXPERIENCE

Electronics Design Intern, Esensors Inc. Aug 2017 - Dec 2017

Designed a wireless vibration sensor as a part of a Home automation system that detects any vibration or motion.

Tested the circuit for its functionality by performing simulations and implementing hardware.

Developed the PCB schematic and layout design in Autodesk Eagle.

Assembled and tested the functionality of various sensors in Laboratory using Oscilloscope, DVM and VNA.

Programmed the Adafruit Trinket to implement communication between the trinket and the RF transceiver.

GRADUATE RESEARCH Feb 2017 - May 2017

Design and construction of a level crossing analog to digital converter and studied its signal to noise ratio.

Analysis of noise shaping characteristics of various ADC’s by simulating designs in Matlab and Cadence.

ANALOG/MIXED SIGNAL DESIGN

Design of a Low Power Two Stage Operational Amplifier of spice model in MATLAB using MOSEK in TSMCO25 Technology

Designed a 2-stage opamp achieving area optimization with a gain=78.5 dB, GBW=10 MHz, phase margin>60 degrees.

VLSI Chip design of CCO based ADC in AMI06 Technology

Developed a 4-bit current controlled oscillator based analog to digital converter in Cadence.

Implemented a DPLL architecture providing a first order noise shaping with a signal to noise ratio of 48dB.

Full Custom Physical Layout IC Design of a Linear Voltage Regulator using Cadence in AMI 16 Technology

Modelled a schematic and layout of a linear voltage regulator which supplies a constant 2.5 Volts, including blocks of a power pass transistor (125mA,300mW), current sink and widlar bandgap reference (1.2 V, 300 uA)

Performed DRC check, LVS match, netlist extraction and simulations in Cadence virtuoso, spectre and Layout.

Analysis and Design of a Digital Phase Locked Loop in AMI06 Technology

Analyzed and studied the design of a digital phase locked loop and then implemented the design in cadence.

Constructed PFD, Charge pump, Loop filter and VCO stages and performed simulations to verify design performance.

DIGITAL DESIGN

Collision Detection in 3-D Printing in Verilog using Xilinx ISE 14.7

Implemented a computer architecture using Verilog to detect malicious codes in 3-D printing.

Used layer-by-layer approach to determine if a line segment is printed twice to avoid collision in 3-D printing.

Design and Verification of a 2x2 Ethernet switch in System Verilog

Designed a 2x2 Ethernet switch using system Verilog.

Performed the verification of the design by creating a test environment.

Implementation of a 16-Bit RISC Processor in Verilog using Xilinx ISE 14.7

Developed a 16 bit unpipelined RISC processor in Verilog using Xilinx ISE 14.7.

Programmed an instruction set that included memory access, data access and control flow instructions.

CLEAN ROOM/MICROELECTRONIC FABRICATION LAB PROJECT/SKILLS

Fabrication of a Solar Cell

Utilized Autocad as a tool to design a photomask for a solar cell and fabricated it in a clean room.

Lab Equipment skills: Ellipsometer, Surface profiler, E-beam evaporator, RIE etcher

TECHNICAL SKILLS

ASIC Design: Layout, DRC, LVS, Netlist Extraction, Verilog, VHDL, RTL coding, synthesis, system Verilog, Xilinx FPGA design

Analog/Mixed-signal design: Op amps, Linear voltage regulator, Band gap reference, LNA, Mixers, ADC/DAC, PLL, SRAM, Oscillator

Physical Design Flow: Floorplanning, Placement and routing, Timing analysis, Clock Tree synthesis, DRC, Parasitics extraction

PCB Design: Eagle, Altium, SMT, Soldering, Logic Analyzers, Oscilloscope, Function Generator, DVM, DFM-DFT guidelines, BOM

Wireless Interface/protocols: SPI, I2C, UART, USB, Bluetooth, WiFi

Programming skills/Software: C, C++, Python, Xilinx ISE, LTspice, PSPICE, Arduino, Raspberry Pi, NI Multisim, NI LabVIEW

EDA Tools: Cadence (Virtuoso XL, Spectre and Layout), ADS, MATLAB

CERTIFICATIONS

VSD-Physical design flow, SOC Verification using System Verilog, Build OVM and UVM test benches from scratch



Contact this candidate