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Engineer Design

Naperville, Illinois, United States
April 20, 2018

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Peter C. S. Tsay

**** *** **** **. ****: 630-***-****

Naperville, IL 60563


Extensive FPGA, ASIC and digital circuit design experiences from concept through design to full production, qualification testing and manufacturing support. This includes many successful projects in wide ranging of industries with products from mobile/telecommunication to aerospace/defense system.

In-depth working knowledge of industry accepted EDA/FPGA tools such as those from Xilinx, Intel/Altera, Lattice, Synopsys, Mentor Graphic and Cadence. Excellent analytical, technical, communication and leadership skills required to carry projects from conception to successful completion. Good team player and skilled communicator with proven track record in resolving difficult and complex issues between functional groups such as R&D, manufacturing, systems and marketing. Excellent credential from prestigious engineering school and top university.



Principal Staff Electrical Engineer, Global Product Development

Primary responsibilities include FPGA prototyping (using Xilinx, Intel/Altera, Lattice) and custom ASIC and proprietary IP development from concept, requirements, specification to RTL (using Verilog/System Verilog and VHDL) design/implementation, integration and functional simulation/verification. Implementation of UVM and System Verilog Assertion methodology. Project highlights:

Neural Network Processor ASIC (Process technology: TSMC 16 nm FinFET):

Worked on the architecture and specification requirements for an embedded AI (Artificial Intelligence), ML (Machine Learning), and Vision Processing System-On-Chip with CNN (Convolution Neural Network) engines for object detection/identification, situation awareness, natural language speech processing and Cryptographic engine with AES encryption to prevent side channel attack and privacy protection.

Integration of high speed serial interfaces: PCIe Gen 3, USB 3.1, eMMC, Gigabit Ethernet, two MIPI D-PHY/CSI for camera interfaces, Dual Core ARM Cortex A53 with TrustZone technology, I2C, I2S, SPI and power islands.

Partnership with Toshiba Semiconductor/TSMC as the Foundry Integrator/Aggregator and Synopsys as the primary IP vendor.

FPGA prototype development using Synopsys HAPS 80 platform using 4 Xilinx UltraScale FPGAs for functional verification before ASIC tape out. Partitioning of the ASIC design for verification and co-development of test platform requirements with Synopsys/Toshiba.

Gbit Ethernet Design Targeting Latest Xilinx UltraScale FPGA:

Designed 10 Gigabit Ethernet using latest Xilinx Kintex UltraScale XCKU040 FPGA and Vivado version 17.4

10-Gigabit Ethernet PCS/PMA with GTH transceiver running at 10.3125 Gb/s line rate.

Contained Ethernet traffic payload generator and performance monitor.

Monitor for bandwidth utilization on transmit and receive AXI-4 data stream interface of the 10-Gigabit Ethernet MAC IP Core.

AXI based design with the MicroBlaze processor as the host to measure statistical eye diagram and bit error ratio (BER).

Using Teledyne LeCroy Scope for eye diagram measurement for signal integrity check.

PETER TSAY, 630-***-**** (continued) PAGE 2

FPGA development for Google Tango AR (Augmented Reality) application:

FPGA design to accomplish detection of Time-of-Flight (IR emitter and ToF sensor camera – 160 pixels x 120 lines, RAW 12) for depth perception.

Fisheye camera (640 pixels x 480 lines, RAW 10) data path to combine with gyroscope and accelerometer data to estimate x/y/z+yaw/pitch/roll for motion detection

5 Mps RGB camera data path to multiplex into the data stream

Total of three cameras streaming into MIPI CSI/D-PHY interfaces, 4 lanes with total bandwidth up to 10 Gbps.

Successful demonstration at the Mobile World Congress

Display Driver IC / CABC (Content Adaptive Brightness Control) IP development on Xilinx Kintex-7 FPGA:

Prototype design platform using Xilinx Kintex-7 FPGA with embedded processor using SDK/EDK tools that included soft IPs such as AXI bus/components, Video DMA, DDR3 memory controller, PCI Express, HDMI receiver/transmitter and Gigabit Ethernet and other third party IPs and in-house developed IPs.

Evaluation and development of color image processing algorithms and techniques using Matlab/Simulink to develop models for initial simulation and subsequent HDL codes generation via MathWorks HDL Coder and hardware co-simulation and verification using HDL Verifier.

Matlab algorithm development, implementation and verification method using FPGA-In-The-Loop (FIL) click link to :

Successful design and implementation of complex DSP algorithms that involves image segmentation, conversion of RGB to Gray, analysis of color intensity and histogram processing of each RGB pixels, Gamma pixel value adjustment for PWM calculation and LED backlight profile characterization and compensation of each pixel within 6 individual segments of an image of 1920x1080 HD at 60 frames per second for rendering new image with better contrast and less

power consumption via dynamic real-time PWM duty cycle adjustment.

Moto Z Modular phone with Moto Mods (based on Google Project ARA):

Performed feasibility study, vendor selection, trade-off studies, requirements and specification development, implementation, system integration testing of the Toshiba bridge IC.

Evaluation and testing of the MIPI high speed serial M-PHY/UniPro interface with bandwidth up to 6Gbit/lane – eye diagram measurements and pre-emphasis and equalization adjustment.

CUMMINS ALLISON CORP., Mt. Prospect, IL 2011 – 2012

Manufacturer of advanced imaging systems for financial institutions and gaming industries

Senior Electrical Hardware Design Engineer

Principal hardware FPGA design engineer to architect and design next generation imaging platform for currency and checking processing system for banking and gaming industries:

Design advanced imaging system using Altera FPGA that interface with Optical and Infrared sensors for high speed imaging capture and processing at 2 Mega Pixels/frame and 27 frames/second.

Design System On-Chip FPGA that interface with dual cores TI DSP TMS320C6657 via Gen 2 PCIe, Serial Rapid IO and DDR2/3.

Evaluating MIPI, SRIO and PCIe soft IP for adaptation into FPGA for interfacing to various TI OMAP DSP chips.

Perform feasibilities and architecture and cost trade-off studies for DSP processor selections.

PETER TSAY, 630-***-**** (continued) PAGE 3

NORTHROP GRUMMAN CORP., Rolling Meadows, IL 2004 – 2011

A defense contractor.

Senior Digital Hardware/FPGA Design Engineer, Defense System Division, Electronic System

Primary responsibilities include design and development of FPGA and digital circuits for the Electro-Optical/Infrared (EO/IR) surveillance and targeting system, electronic counter-measurement and self protection system for the U.S. and allies military fixed wing aircrafts:

Working with system, software and other hardware engineers to develop initial FPGA design requirements, conducting feasibility study, getting project approval, conducting preliminary and critical design review (PDR/CDR) for both internal and external customers.

Developing FPGA design specification with flow down system requirements, implement RTL design, perform functional simulation, verify functionalities at the board and system level in accordance to the design requirements. Assist in system integration test activities and flight test.

Designed System-On-Chip FPGAs serving as communication hub, video routing/image processing/display, time and telemetry acquisition using Xilinx Virtex devices.

Designed FPGA that interface to a turret containing two Electrical Optical (EO) Sensors with 12-bit Bayer (1280x1024x30 Hz) and one Infrared Sensor (IR) with 14-bit intensity (640x512x30 Hz) and video data sent via backplane at 3.125Gb/s high-speed serial interface.

Implemented FPGA design capable of connecting and processing any 8 image processors display IOs with embedded/packetized video, processor and routing information via 15 individual Xilinx

high speed serial IO (Rocket I/O) links at 2Gbit/s using Aurora link protocols and mapped/sent data to 6 HD-SDI (SMTPE 274M-G, 2200x1125x30Hz) compliant output display monitor links.

Used Xilinx and Agilent E5910 Serial Link Optimizer tool to insert Chipscope Controller/Analyzer and Internal Bit Rate Tester (IBERT) to monitor signal/data integrity on each backplane high speed serial link trace. Evaluated and optimized each Rocket I/O MGT’s internal pre-emphasis/equalization setting and then back-annotate setting back to the design to obtain best eye diagram.

FPGA design that provides a hardware implementation of an IR-based missile detection algorithm with digitized video input (two pixel arrays red/blue at 320x320) and with output of IR threat list. Interfacing to Readout IC(ROIC) and Analog to Digital Converter(ADC) as well as PCI Express bus and DMA Engine module.

Various FPGA designs which including QDR SRAM interface, high speed serial links such as PCI Express, Gigabit Ethernet, FIFOs, RAMs, DMA block, CRC, 8B/10B encoding/decoding, temperature sensor, A/D and D/A converters, Platform Flash to store VCO temperature compensation data and dual FPGA firmware images to facilitate field upgrade.

Working with board design engineers on the analog circuitries which interface to the FPGA.

MPC PRODUCTS CORP., Skokie, IL 2003 – 2004

An aerospace and defense contractor company.

Embedded System Design Engineer, Digital System Division

Hardware Design Engineer for NASA’s SOFIA Project (Stratospheric Observatory For Infrared Astronomy):

Designed digital electronic embedded system using Motorola’s Power PC, Flash RAM, SRAM, A/D, D/A, R2D and Resolver position sensing and various monitoring circuits to control the mechanical actuation system for the telescope assembly mounted on a Boeing 747.

Create and test analog and digital circuits using ORCAD schematic entry tool and PSPICE.

Served as a technical lead in the digital electronic development and transition to flight test ready hardware.

PETER TSAY, 630-***-**** (continued) PAGE 4

Defined and developed test codes to verify system functionalities and compliance with design requirements and other regulatory requirements such as DO-160 and DO-254.

Assisted in system reliability validations and other product testing function.

TELLABS, INC., Naperville, IL 1992 – 2003

A major telecom equipment vendor.

Senior Hardware ASIC Design Engineer, VLSI Design, Optical Networking Group (1999–2003)

ASIC Design Project:

Architected, designed and led a group of engineers to complete Tellabs’ first generation of highly integrated System-on-Chip ASIC with over six million gates using the 0.18u CMOS 5 layers metal technology.

Actively led and contributed at every stage of the project from design specification, RTL coding, synthesis, functional verification, physical design with placement/routing using Avanti Apollo II and static timing analysis to final tape out.

Designed fully Sonet compliant ASIC capable of interfacing with four STS3/3Cs or one STS12/12C with ability to process and terminate STS and VT level plus performance monitoring capabilities. This chip was targeted for Tellabs 5500 Optical Digital Cross Connect product.

Achieved first time success tape out using Customer-Owned-Tooling (COT) model and 0.18u Passport Library. The adoption of this methodology allowed multiple vendors sourcing,

significantly increased the density of the port shelf, drove down the piece part cost and improved overall profit margin.

Efficiently and diligently managed and resolved technical issues among team members and across different organizations, such as firmware, hardware, systems and marketing groups.

FPGA Design Projects:

ASIC proof-of-concept implementation via multiple FPGA partitioning using Xilinx and Altera FPGA for regression and new function implementation as part of ASIC pre-tape out requirement.

Worked on ATM design project using Lattice FPGA ORT8850 FPSC. Responsibilities included development of design specs, RTL/Behavior coding (VHDL/Verilog), synthesis using Synplify Pro, placement and routing using Lattice ISP Lever tool

Hardware Engineer (SMTS) (1992–1999)

Involved in several chip design tasks ranging from RTL coding, synthesis, verification, test scan insertions, vector generations, and test coverage analysis and test vectors simulation.

Involved in component failure analysis; working in conjunction with manufacturing and foundry vendor to develop more efficient and accurate screening process. Resulted in significant improvements in reliability and overall yield.

Successfully designed and validated first boundary scan (JTAG) implementation at Tellabs and later adaptation of this technology across all ASIC chips at Tellabs. The addition of testability resulted in significant reduction in test time and quicker delivery of product to customers.

MATSHUSHITA COMPUTER COMPANY (a major consumer electronics company) 1991 – 1992

Project Engineer

Main technical leader in charge of transferring design technology from Solbourne Computer in Colorado to Matsuhushita in Franklin Park, Illinois. Responsible for resolving issues ranging from manufacturing tests, training of technicians to production processes and parts reliabilities.

Served as liaison between R&D center in Solbourne to testing and manufacturing center in Matshushita. Ensured smooth production of UNIX desktop and server workstation.

PETER TSAY, 630-***-**** (continued) PAGE 5


Master of Science in Electrical Engineering

University of Illinois at Chicago

Bachelor of Science in Electrical Engineering

University of Illinois at Urbana-Champaign



VHDL, Verilog, System Verilog, Verilog Assertion, UVM for ASIC/FPGA verification

Programming Languages:

C/C++, OpenCL, Python, Java, Perl, Tcl, Assembly

Operating Systems:

Linux/Unix, Microsoft Windows

Synthesis Tools:

Synopsys Design Compiler, Synplify Pro for FPGA

Timing Tools:

PrimeTime and various other FPGA tools

Physical Design:

Synopsys/Avanti Apollo

Logic Simulation:

Mentor Graphics Modelism/QuestaSim

Design for Test:

Synposys Tetramax

FPGA tools:

Board Design tools:

Xilinx ISE/Vivado, Xilinx EDK, Xilinx System Generator, Intel/Altera Quartus, Altera SOPC Builder, Lattice Diamond

Cadence ORCAD schematic entry, PSPICE, Green Hill Emulator

System Modeling tools:

Source Control tools:

Technology and Standard:

MATLAB/Simulink, HDL Coder, HDL Verifier

ClearCase and ClearQuest and Door

Deep Learning, Machine Learning, Caffe and TensorFlow

PCIe Gen 3.1, USB 3.1, VESA USB-Type C, Gigabit Ethernet, eMMC, Intel Thurderbolt, DisplayPort, HDMI, I3C, I2S, LPDDR4, MIPI D-PHY, M-PHY, CSI, DSI, UniPro

AES Encryption, HDCP, DRM


U. S. Citizen with active government security clearance granted

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