semiconductor manufacture, foundry, product,reliability, quality assur

Pao Chou

*rd Floor, No. **, Lane 11-408-*******

Dongshan Street 011-886-0965374745

Hsinchu, Taiwan, ROC *******@*****.***

WeChat/ Line ID: pao1698

OBJECTIVE

Staff Foundry Engineer (can be relocated to USA)

SUMMARY of QUALIFICATIONS

Engineer with 20+ years of experience in IC process, design mask tape out, TSMC/UMC foundry interface, assembly, product qualification, reliability test, SMT, and quality assurance.

Knowledgeable in efficient development of IC design from product through mass production.

Experienced with reliability qualifications; ESD and Latch-up, HTOL, package level 3.

Hand on Experience in device characterization for Non-Volatile Devices, Flash and EEPROM.

QA audit team member experience from IC manufacture process through SMT process.

EDUCATION

Arizona State University (Tempe, AZ)

M.S. Electrical Engineering

National Central University (Chung-Lee, Taiwan)

B.S. Physics

WORK HISTORY

ITRI (Hsin-Chu, Taiwan) Current

Consultant

Lead multiple projects focusing on advanced technology development, reliability study of new materials, and new innovation.

SVP-Tech (Fremont, CA) 2011 to 2014

RMA Warehouse Manager

Responsible for QA activity of shipping receiving, package assembly, RMA test and repair on Camera, Android smart phone, Tablet PC, photo scanners, mini projector, etc.

Wintec Industries (Milpitas, CA) 2005 to 2010

Manufacture Process Engineer Acting Production Manager

Led and supervised 35 staff for PCB assembly, SMT manufacturing, testing, QC inspection, soldering, products including DRAM memory module, CF card, SSD, modern, and Eye-FI.

Led ISO quality control of SMT manufacturing, inspection, testing, rework for all modules.

Assured proper handling and processing carried out of thermal profiles, screen printing programs,

Stencil quality control for each product.

Led RMA troubleshooting, SPD review, schematics review, failure analysis, repair, burin-in, etc.

PLX Technology, Inc. (Sunnyvale, CA) 2001 to 2005

Sr. foundry Engineer

Coordinated in collaboration with Design, Testing, Marketing, Reliability, Foundry, Assembly to develop new product from cost, feasibility, qualification through production in lower lead time.

Set up PCI-X bridges data sheet specifications based on product capability, system, and characterization.

Performed risk assessment to support marketing sales using established reliability techniques to identify potential reliability concerns.

Managed product qualification tasks according JEDEC and MILSTD, lined on QA ISO requirements.

Completed load board design, product qualification and maintained quality control in production.

Conducted reliability test, including ESD, Latch-up, HTOL, C-SAM, temperature cycle, 85/85, pressure pot, E-beam failure analysis, de-cap, back lapping, chemical treatment, SEM, X-ray.

Conducted competitive benchmarking in assembly package design and materials across suppliers.

Developed package substrate requirements and defined cost estimated to support marketing group.

Completed robust package design for manufacturability and reliability on TBGA 15x15 160ball substrate, BGA 27x27 380ball substrate, QFP 30x30 208P with ITDS thermal simulation.

Interfaced with SPIL and ASE for package design and assembly manufacture yield improvement.

Interfaced with TSMC technical, tape out, mask making, production ramp up, yield improvement.

Responsible for design tape out procedure, including design rules DRC, ERC, LVS review.

Responsible HiNT operations manager of design, foundry, assembly, product, and test merged into PLX portfolio.

LSI-Silterra (Malaysia) 1999 to 2001

Staff Process Integration Engineer

Achieved LSI 0.18um technology, thin film, diffusion, STI, CMP, etch process transfer to Silterra.

Performed QA audit activities to validate process in compliance to specifications and measurement.

Run test wafers and cross metric split lots to complete process calibration and process flows validation.

Interfaced with Engineering and Operations to ensure process transfer to production accordingly.

Transferred EDA, TCAD tools, and layout viewer from LSI to Silterra.

OPTi Inc. (Milpitas, CA) 1996 to 1999

Foundry Operations Manager

Coordinated in collaboration with Foundry, Design, Assembly, Product, Testing, Reliability, Marketing, to develop product from cost, feasibility, qualification to production in short lead time.

Provided parametric test design, IO cell layout for reliability test, and yield improvement.

Coordinated new BGA package processes with assembly and testing at ASE in Taiwan.

Transferred 0.8um Silicide process from IBM USA facility to TSMC Taiwan facility.

ROHM Corporation. (San Jose, CA) 1989 to 1996

Engineering Section Manager

Completed comparative studies, cost estimates, installation, characterization, optimization for the best yield of equipment including plasma processing, wet processing, defect inspector.

Developed process of lithography, etch, implant, thin film for non-volatile EEPROM and Flash.

Led integration on electrical test and compiling of device performance for process optimization.

Led process sustaining team for equipment monitor, PM, production and engineering support.

Optimized all plasma etch process on Lam rainbow, poly/nitride/ox, metal etch.

Optimized process flows through devices measurement and devices simulation with TCAD tools.

Achieved yield improvement 30% through DOE process optimization, defects and quality control.

Conducted low yield failure analysis by chemical treatment, SEM, EDX, and X-ray inspection.

Achieved yield 30% improvement from die saw, SOIC assembly defects reduction at EXAR.

Established defect base line f (threshold VS particle size) for all plasma etchers with statistics.

Promoted as manager and Transferred 3um NMOS EEPROM process to CMD at Phoenix, AZ.

Integrated Device Technology Inc. (Salinas, CA) 1987 to 1989

Senior Process Sustaining Engineer

Achieved yield improvement 20% by running equipments at higher efficiency performance ramp rate, lower contaminations, and higher throughput at night shift for all plasma etchers.

Spectra Diode Laboratory. (Santa Clara, CA) 1985 to 1987

Quality Assurance Engineer

Responsible for quality assurance program, compiling spec of MOCVD GaAs III-V compound Laser diode process, Hermetic assembly package and burn-in test.

American Microsystems Inc. (Santa Clara, CA) 1983 to 1985

Pilot line Photolithography and Etch Process Sustaining Engineer

Worked with R & D group on process transfer and yield improvement.

Implemented SPC control chart on lithography and plasma etch process to maintain quality.

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