C, C++, Assembly, SystemVerilog, CUDA, MATLAB, Python, Perl, UVM

Jay Udani

**********@*****.*** 919-***-**** https://www.linkedin.com/in/jay16udani/ Raleigh, NC 27606.

OBJECTIVE:

To work with the engineering department as a Firmware Engineer, where my education experience, technical and creative skills will help develop and drive your products to remarkable success.

EDUCATION:

North Carolina State University – Masters in Computer Engineering May 2018

Relevant Courses: Computer Design, Digital ASIC Design, Advanced Computer Architecture, Embedded Systems Design

Architecture of Parallel Computers, Operating Systems Design, Internet Protocols

University of Mumbai – Bachelors in Electronics & Telecommunication Engineering June 2016

SKILLS:

Programming Languages: C, C++, Assembly, Verilog, SystemVerilog, CUDA, MATLAB, Embedded C, Python, Perl, Tcl, Shell

Operating Systems: Linux, Windows

Software: QuestaSim, ModelSim, Veloce, Synopsys Design Compiler, LabVIEW, PSoC Creator IDE, ARM Mbed IDE, Keil IDE

Hardware: FRDM – KL25Z, PSoC4, BLE, x86, ARM, JTAG, Logic Analyzers

PROJECTS:

North Carolina State University:

Operating Systems Design: August – November 2017

Implemented Shortest Time to Completion First and Multi-Level Feedback Queue scheduling algorithms in XINU

Successfully implemented the test and set atomic instruction in assembly, deadlock detector using Banker’s algorithm and priority inheritance protocol in XINU. Also implemented trylocks to show how their use can avoid deadlocks

Successfully designed and implemented virtual memory and demand paging for XINU

Cache Coherence Protocol Simulator for Shared Memory Multiprocessors October – November 2017

Modeled and implemented a cache simulator for the Symmetric Multiprocessors systems. The simulator implemented the MSI, MOSI and MOESI protocols for cache coherence across parametrized number of processors with distributed L1 caches

Implemented another cache coherence simulator for Distributed Shared Memory based Multiprocessors to measure the performance of MESI protocol for given cache hierarchy. The directory information was stored either as Full-Bit Vector directory (FBV) or as Simplified Scalable Coherent Interface (SSCI) directory

Benchmarked the performance of these protocols in terms of number of cache misses and bus traffic using SPEC suite

Optimizing Energy Consumption in FRDM KL25Z April 2017

Built a power and energy model to help serve as a guide for design and optimization process for the KL25Z mbed board which was configured to blink the on-board LED as per the tilt angle detected

Increased the system energy use on using code optimizations, clock gating, low power modes, PWM, wake up on activity detection, increased data rate for I2C communication link, and deep-sleep modes

Distributed Web-Caching using OpenFlow November 2016

Implemented a distributed, multi-threaded web caching system using OpenFlow protocol on GENI testbed to achieve a 50 % faster access to frequently requested web content by caching them locally in cache server

Responsible for configuring the POX controller as a L3 learning module to enable it to automatically map the IP’s and MAC, install flows in the OVS switches, and flood & respond to the ARP requests

Implemented a JSON file which maintained the state of the cache server in case the server goes down

Out-of-order Superscalar Processor Simulator November 2016

Designed and implemented a simulator for a 9-stage Out of Order superscalar processor, based on Tomasulo’s algorithm

Implemented an I-cache for the fetch stage along with a prefetching unit to reduce the miss rate and increase the IPC

Estimated the IPC and compared the results for the different combination of width, reorder buffer size and queue size

Cache Hierarchy Simulator September 2016

Modeled a two-level cache hierarchy simulator with four replacement policies (LRU, pseudo-LRU, FIFO and Optimal) and three inclusion policies (Inclusive, Exclusive and Non-Inclusive)

ACHIEVEMENTS:

Recipient of J.R.D TATA - Merit Based Grant in 2015

Recipient of Maharashtra State Board Scholarship in 2012

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