Electrical Engineering Design

ANIKET M. HAJARE River drive south, Jersey City, NJ

*******@***.*** linkedin.com/in/anikethajare

Phone: 469-***-****

EDUCATION

Master of Science in Electrical Engineering GPA:3.57/4.00 Southern Methodist University, Dallas, TX May 17

Courses: Advance VLSI, Formal Verification, Computer Architecture, Digital System Design, Transistor Integrated Circuits Bachelor of Engineering in Electronics & Telecommunication GPA: 3.50/4.00 University of Mumbai, India Jun 15

TECHNICAL SKILLS

Programming Languages: Verilog, SystemVerilog, Python, Perl, C, C++, Java, MATLAB, Object Oriented Programming

Electronic Design Software: Cadence Virtuoso 6.1, Synopsys VCS, Altera QuartusII, Cadence SimVision

Protocols Knowledge: APB,AHB, AHB Lite, SPI, I2C and UART CERTIFICATIONS

Verification Academy: Basics and Advanced UVM, Udemy: Verification using UVM, Python Bootcamp ACADEMIC PROJECTS

APB Interface: Sep 17

Developed from scratch the UVM constraint random verification test environment for APB interface. Generated APB transactions using Test, Sequence, Environment, Agent, Driver, Monitor and Sequencer. Verification of a Packet based Protocol using System Verilog based Test Environment May 17

Developed constraint base verification environment using SytemVerilog to verify a packet based protocol DUT with interfaces, sequencer, assertions, drivers, transactions, scoreboards in Synopsys VCS RTL Design and Verification of Asynchronous FIFO Apr 17

Designed and performed verification of Asynchronous 8-bit FIFO in SystemVerilog using Synopsys VCS

Created various modules for Memory, empty & full conditions, Synchronizer module and gray code counters to resolve metastability during clock Domain crossing

Design & Verification of a Memory using UVM Feb 17

Developed a constraint random verification environment for verification of a memory

Verified memory by building a transaction, sequence, sequencer, driver, monitor, scoreboard, agent and interface Design of a pipelined MIPS processor with data forwarding and hazard detection: Dec 16

Designed & Implemented a balanced five stage pipelined MIPS Processor in Verilog with data forwarding and hazard detection unit using Altera QuartusII

8bit 3x4 Matrix Multiplier Dec 16

Designed 3x4 matrix multiplier in Verilog RTL using datapath and controller on Altera QuartusII

Accomplished initiation rate of 19 clock cycles and a latency of 28 clock cycle using multiplier accumulator unit Newton-Raphson Dec 16

Designed synchronous controller in Verilog RTL to compute the numerical inverse of the 8-bit unsigned number ASIC Phase Shifter Dec 16

Developed a wide-range (25 ns), high-resolution (50 ps) clock phase shifter

Phase shifter divided into Fine Shifting Logic(FSL) and Coarse Shifting Logic(CSL) ASIC 16x16 Crossbar Switch: Dec 15

Designed 16x16 Crossbar switch on Cadence Virtuoso with multiplexer as a basic building block

Accomplished Schematic Testing, Layout, DRC, LVS, QRC and data rate of 1.2 Gbps with latency of less than 1ns Equivalence Checking and Variable Reordering for Binary Decision Diagram: Mar 16

Implemented Formal Verification equivalence technique to compare combinational circuit for functional equivalence Reachability Analysis of Finite State Machines: May 16

Implemented Monolithic Transition Relation for reachability analysis using CUDD for reachability of FSM EXTRA CURRICULAR

Technical advisor, Student’s Council, University of Mumbai

Responsibilities included event planning and organizing annual cultural festival May 13-May 14

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