Engineer Design

KANAVA SAIT A

****, ****** **, *** ****, CA *****

Email ID: **********.*@*****.***

Cell Phone: +1-669-***-****

Professional Synopsis

HCL America Inc: Technical Lead May 2014 - Present

Product: FLASH Array Network Storage Systems (Vexata Inc.)

Responsible for preparing high level & low level design documents by doing analysis, simulation and component selection based on board requirements.

Responsible for schematic design of boards in the storage system.

Prepared layout constrain document and worked along with layout team for component placement and routing. Coordinated with mechanical team for thermal consideration and fitment.

Test document preparation and testing- Board bring up, functional level validation, design level validation, system integration testing, bug tracking and closure

Hands on experience in high speed interfaces i.e:10GKR, PCIe Gen 3, DDR3, mSATA and low speed interfaces i.e: I2C, SPI, UART, JTAG, RS-232

Having experience in high density FPGA (Xilinx), PCIe switch and multi core processor based product architecture design and development. Also, having experience in designing products with memories i.e: DDR3/DDR2, NAND/NOR Flash memories, eMMc, EEPROM, NVMe/ Msata SSDs.

Hands on experience in power solution/power architecture- DC/DC converter, LDO, Hot swap design for high current rating.

Have done compliance testing for DDR3/DDR2 and 10GKR interfaces

Executed test automation scripts in Python and modified test attributes for different test cases.

Have done board level analysis for power, derating, stress, logic compatibility, power integrity.

HCL Technologies Ltd., India: Lead Engineer May 2012 - May 2014

Worked on Schematic Drawing, Design Analysis, Component selection and list preparation, Layout support, Device Verification Testing, Hardware-Firmware testing, System level testing and debugging.

Hands on experience in Design Validation and Electrical Verification Testing of High Speed Interfaces such as DDR2, DDR3, SGMII, Ethernet PHY, SRIO, LVDS, SPI, I2C and MDIO signals.

Experience in handling lab equipment’s such as High Bandwidth Oscilloscopes & its probes, Vector Signal Generator & Analyzers, Logic & Protocol Analyzers and Network Analyzers.

Prepared Hardware-Firmware Interface document, Layout constrain document, Test plan and Test report for board validation.

Awarded Outstanding Achiever Award & Livewire Performer Award consecutively for 3 years.

Data patterns (India) Pvt.Ltd: Design Engineer July 2010 - April 2012

For VME and PMC standard modules, supported in component selection, schematic design, design analysis, layout support, test jig preparation for automation testing and test document preparation.

Hands on experience in VMEbus, PCI bus, FPGA, QPSK modulators, ADC, DAC and ADS simulation.

Education

Completed bachelor’s degree in Electronics and Communication Engineering in the year 2010 at Anna University(India) with 79%

Skill Summary

Skill Area

Hands on Experience and Knowledge

Product Schematic Design

Network storage, Mobile signal processing unit, VME and PMC modules

Design Analysis

Power stability, Power sequence, Power Integrity, Voltage compatibility, Part stress analysis, Clock scheme and Reset scheme.

Scripting Language

Python, Bash

Software Tools

ORCAD Capture, Allegro PCB Editor, HyperLynx Mentor Graphics, ADS Simulator & LT spice IV, Expedition PCB

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