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Design Engineer

Gainesville, Florida, United States
November 29, 2017

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Seeking Full-time Positions in Digital Design & Verification (Availability - October 2017)

+1-352-***-**** Gainesville, Florida EDUCATION

M.S. in Electrical and Computer Engineering, University of Florida May 2017 GPA - 3.36 /4.0 Coursework: VLSI Circuits and Technology, Advanced VLSI Design, Analog IC Design 1, Foundations of DSP, Mixed Signal IC Test 1, Reconfigurable Computing, Computer Architecture, Fault-tolerant Computer Architecture, Computer Communications, Wireless Communication.

B.E. in Electrical and Electronics Engineering, Anna University (India) April 2014 GPA - 8.23 / 10 Coursework: VLSI Design, Data Structures and Algorithms, Linear Integrated Circuits and Applications, Digital Signal Processing, Digital Logic Circuits, Power Electronics, Microprocessors and Microcontrollers WORK EXPERIENCE

Research Volunteer – IC Testing Lab, University of Florida May 2016 – Present Designed and Developed Experiments for ATE-based testing of resistors, capacitors, LDO regulators, Op-Amps and Temperature sensors for graduate-level class; the testing was done on NI Mid-Level ATE; this experience helped me understand the process of developing testcases for ATE-based testing using NI LabVIEW and TestStand. Systems Engineer Trainee - Database Administrator, Infosys Ltd. December 2014 – April 2015 Underwent Industrial training in Database Administration using Oracle 11g, Java and MySQL. Intern - Embedded System Design Lab, Anna University (India) July 2014 – September 2014 Trained in working & functioning of PIC and ARM MCUs using MPLAB and applied my training in a series of assignments. This experience allowed me to get out of the textbook and learned to develop practical solutions for real-world problems. TECHNICAL SKILLS

HDLs & Programming Languages: VHDL, Verilog HDL, C/C++, Java, PERL (Scripting). Development Tools: Cadence Spectre, Virtuoso, Encounter, Hierarchy Editor, Synopsys Design Compiler, Mentor CalibreDRV, Synopsys Hercules, Nettran, MATLAB, MPLAB, LabVIEW, ModelSIM, NI TestStand, Xilinx Vivado. ACADEMIC PROJECTS

Design and Implementation of an All-Digital Phase Locked Loop (ADPLL) in 240 nm node

• Texas Instruments’ architecture was used and a locked state was achieved within 100 cycles of reference clock.

• The circuit was designed using Verilog HDL and RTL to GDSII flow (using Synopsys DC & Cadence Encounter) was followed for Gate-level Synthesis and Automatic Place and Route (APR).

• Basic block level and top-level verification was performed using testbenches and models written in Verilog. Gate- level and post-layout simulation were performed with Cadence Spectre using Cadence Hierarchy Editor. Design of a 2-Stage Miller Compensated Fully Differential Amplifier with Common Mode Feedback (CMFB)

• The differential amplifier was designed with CMFB and Miller Compensation to set the desired output common mode voltage and increase stability of the circuit respectively.

• The circuit was designed with a Power Constraint of 5mW, (W/L) of all transistors less than 200, Unity Gain Bandwidth

(UGBW) of 275 MHz, Phase Margin of 62.2 and a Gain of 60 dB at room temperature.

• Layout, DRC and LVS were done with Virtuoso and gate-level and post-layout simulation with the help of in Spectre simulation environment.

Implementation of a Custom Circuit for 1-D Convolution on a Xilinx 7 Series FPGA

• A pipelined circuit for 1-D Convolution was designed with sliding window buffers to increase memory bandwidth and enable maximum loop unrolling.

• External DRAMs were used for kernel and signal data, leading to Clock Domain Crossing issues, which was resolved by using Synchronizers like Dual Flip-Flop, Handshake and FIFO.

• The circuit was designed using VHDL and implemented on a 7 Series FPGA using Xilinx Vivado. Design of a 16-bit SRAM System in 240 nm Technology

• The Memory System’s components – 6T SRAM Cell, Pre-charge Circuitry, Sense amplifiers and Decoders were designed with appropriate transistor sizing for high-speed operation & read/write stability.

• Noise Margin Analysis, block-level and top-level simulations were done using MATLAB & Spectre; Place & Route

(PAR), DRC and LVS were done using Cadence Virtuoso. Implementation and Evaluation of Victim Cache Configurations to improve Hit Rate

• A Victim Cache was implemented between L1 and L2 cache to improve Hit Rate and its performance was evaluated for multiple associativities, block sizes, cache sizes.

• Architectural modifications were made in C (Linux Environment); the new design was tested using SimpleScalar Simulator and the best configuration was determined using MI & SPEC2000 (Embedded System Benchmarks). Analysis of Software Fault Tolerance Techniques on PowerPCs using SIMICS and DrSeus

• Developed software fault tolerant techniques incorporating SWIFT, Software Rejuvenation, Acceptance tests and Redundant Execution for Edge & Corner Detection Applications (in C

• The Application and Fault Tolerance Techniques were implemented on PowerPCs; faults were injected using DrSeus and the performance of fault tolerant techniques were evaluated using SIMICS simulator.

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