Sign in

Engineer Electrical Engineering

South San Francisco, California, United States
November 27, 2017

Contact this candidate


Avi C. Patani

**** ****** **, *** ***, Santa Clara, CA 95051 C: 562-***-**** SUMMARY

Electrical Engineer adapt at all aspects of computer engineering, including hardware and PDA design. Looking to obtain a position of Electrical Engineer, which effectively contributes to my and the organizations growth. EDUCATION

Master of Science: Electrical Engineering Dec 2014 California State University Long Beach,


GPA: 3.5/4.0

Coursework: Linear System Analysis, Advanced Microprocessors and Controllers, CMOS Electronics, Mixed Signal IC Design, VLSI Design, System on Chip design, Microelectronics Bachelors of Engineering (B.E: Electronics and Tele-Communication Engineering) May 2012 University of Mumbai Mumbai, Maharashtra,


GPA 3.3/4.0


• Programming Languages: VHDL, Verilog, System Verilog, RTL and TTL Scripting, Perl, Shell, C/C++, Embedded C, Object Oriented Programming, UNIX (Makefile),

• Tools: Xilinx ISE, Cadence Virtuoso, Modelsim, OrCAD, PSpice, VCS, MATLAB, HSPICE, and Synopsys TCAD, Solidworks.

• Others Specialties:

Verification Methods IC Design Technologies Electrical Engineering Concept UVM, OVM, VMM Mixed Signal Design Amplifier Design Functional Verification Physical Design Op-Amp design DFT and LVS SRAM Design Electrical Circuit Design

Silicon Debugging FPGA Oscilloscopes

Constrained Random Generation NAND Spectrometers

Boundary Scan SSD Controller ADC/DAC Controllers

JTAG Flash Memory Digital Signal Processing

Static Timing Analysis Nano and Micro design AMBA Architecture Failure Analysis Memory Architecture PCI Express

Gate level Simulation CMOS/MOSFET BJT

ATE Design VLSI Design PCB Design


• Test Engineer April 2017-Present

Verily (Google)-South San Francisco

To create test environments and inspect optical lens for depth sensing. To validate the various electrical parameters for in lens circuitry. Provide support to the failure analysis lab and help debug various issues and defects Assist in setting up an automated system for in-house testing and failure analysis. Create processing tools using Matlab and Python for data analysis.

• Lab Engineer Oct 2015-April 2017

Microsoft- Silicon Valley

To create test environments and validate CMOS image sensor pixels for Hololens. Prepare test cases and parameters, setup, and run a broad suite of tests on sensor hardware and systems.

Use prototype boards to validate the sensors in and external environment Provide test data, analyze these data, and provide recommendations that will help to evaluate the CMOS Sensor.

Create processing tools using Matlab to help better understand the sensor behavior.

• VLSI Design Verification Engineer June 2015-Oct2015 SSRLabs,

To design and verify very large capacity memory systems using Verilog and System Verilog Developing and modifying new design or verification IP. Writing and running tests to improve measured coverage. Adding assertions and coverage statements to verification IP.

• Instructional Student Assistant Oct 2012-Dec2013 LAC, CSULB

To tutor undergraduate students in topics related to Math, Physics and Electrical Engineering.

• Training -SINE IIT B Incubation Think Labs, Mumbai, India July 2011. A Certified Course on AVR, Embedded C and RTOS for four weeks. ACADEMIC PROJECTS

• Implementation of Single and Dual Port Memories

Synthesized and verified both memory configurations on 0.5-micron technology using Verilog and then implemented it using Xilinx 14.4.

• Single Port BIST (Build in Self-Test)

Designed a system, which was capable of detecting defects using VHDL and implemented it using Modelsim.

• Design and Synthesis of a RISC Processor using MIPS architecture. Developed a 5-stage pipelined 8-bit RISC processor using System Verilog and implemented it using Synopsys VCS and Synopsys Design Compiler.

• Drive UART using Picoblaze at 50Mhz

System on chip (SOC) implementation of an 8-bit processor that drives UART, it was designed using Verilog and implemented using Xilinx ISE 14.4 and Spartan 3E FPGA.

• Boundary Scan Test

Designed and implemented a boundary scan system to verify ASIC design, using VHDL and was implemented using Xilinx ISE 14.4 and Spartan 3E FPGA.

• Viterbi Decoder

Implemented Viterbi decoder to decode convolution codes using VHDL and it was implemented using Xilinx ISE 14.4 and Spartan 3E FPGA.

• Transaction based SOC Design technique for AMBA AX14 Bus Interconnects. Designed and verified a new verification technique based on AMBA AX14 Bus, using VHDL and UVM

• ASIC Design of a Reversible Multiplier circuit.

Designed and implemented a Reversible Wallace signed multiplier circuit, using Verilog and simulated, also did a LVS and DRC.

Contact this candidate