Engineer Electrical Engineering
Resume:
SUMMARY
Looking for a full-time position as an ASIC/FPGA Design verification engineer
Mixed Signal Verification Engineer with knowledge of methodologies and applications of advanced verification tools
Expertise in System Verilog, UVM and strong verification skills like random and advertising testing and debugging
In-depth knowledge of computer architecture, debug tools, logic design concepts and stimulators like VCS
Hands on experience in UVM, assertions, Functional Coverage, RTL Designing, analysis of code coverage SKILLS
Programming/Scripting languages: System Verilog, UVM, Python, Perl, Verilog, C++, C, VHDL, Embedded C,
Tools/Simulators: Eclipse, Xilinx ISE/Vivado, Altera Quartus, VCS, NCVerilog, GTKWave, Verdi, MATLAB, Modelsim, JasperGold, AVR Studio, MikroPIC, Arduino
Operating Systems: Linux, Unix, Ubuntu, Windows, MacOS EDUCATION
Master of Science, in Electrical Engineering, Specialization- Digital VLSI, GPA-3.8 San Jose State University, San Jose, Dec 2017
Bachelors of Engineering, in Electronics and Communication Engineering, GPA-3.42 Gujarat Technological University, India, June 2015 EXPERIENCE
INTEL CORPORATION, FOLSOM, CA June 2017 – Present
Graduate Intern, Mixed Signal Verification Engineer
Responsible for identifying, implementing and tracking code coverage against product features and test plans
Developing directed/random test cases, debugging failures using spytool to ensure full feature coverage (currently at 91.2%).
Recognized for achieving the expected goal of 90% coverage and documenting details for the team.
Developing and maintaining UVM based co-simulation environment, that include checkers, BFMs, monitors, DPI interface to reference
Responsible for porting assertions and debugging the failures in regression to achieve 97.5% assertion success rate
Utilizing advanced techniques like JasperGold to achieve verification and validation with the highest quality and productivity
Responsible for providing support to the design staff in debugging fixes and eventually finding three major RTL bugs SOFCON INDIA PVT. LTD., INDIA July 2015-Dec 2015
Mixed Signal Intern
Successfully performed serial communication (UART), SPI interface, I2C communication, ADC, RTC using ARM and PIC boards
Presented solutions to calibrate analog models using Cadence and Verilog-AMS
Developed and simulated Embedded C designs using AVR Studio and MikroPic tools
Analyzed and dumped program on Embedded boards and also internally controlled the temperature through temperature sensor
Performed serial hardware interfacing on the ARM board and operating it at various oscillator frequencies ACADEMIC PROJECTS
COMMUNITY BASED CAN VERIFICATION Aug 2017- Present
Collected several CAN transmitter designs and voted out the most efficient design by undergoing verification and coverage analysis
Generating a python script which helps decide the best design based on minimum SVA failure, maximum RTL and functional coverage STANDARD BUS PROTOCOLS Feb 2017
Designed and synthesized CAN bus data transmission protocol using system Verilog
Completed System Verification of SPI bus protocol by UVM, generating sequences using System Verilog SOURCE BASED ROUTER NETWORK Dec 2016
Designed and Synthesized a communication network protocol for data transmission
Proficient use of Verilog HDL and VCS for synthesis, using Python scripting for testing
Successfully performed timing analysis and place and route of the design PID CONTROLLER Nov 2016
A controlled loop feedback mechanism used to calculate erroneous signals in control systems
Designed and synthesized using Verilog HDL in VCS at multiple frequencies and achieved efficient timing analysis ADAPTIVE LMS AND FIR FILTERS Nov 2016
An FPGA based design of 128 tap serial and parallel filter system for noise reduction in image processing
Efficient usage of Verilog HDL for designing in Quartus Prime and QuestaSim Altera for functional simulation CERTIFICATIONS /ACHIEVMENTS
System Verilog Verification: Object Oriented Programming
UVM in System Verilog: Learn the Architecture and Code VIP
Lead a team of four to accomplish the Design of Portable Electronics Lab
Volunteered Technical Fest events, member of Organizing Committee, India 1550 Iron Point Rd,
Folsom, CA-95630
*Open to Relocate
PRAJAKTA ABHAY PRADHAN
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