Engineer Test

Fangzhe Dong

**** ***** ** #*, *** Diego, CA*****, United State, 858-***-****, ************@*****.***

Objective

I'm looking for a full time position as a RF/analog system design and test Engineer, product Engineer.

Qualification

•4 years experiences of new chip bring-up and characterization for high frequency RF circuit including

LNA/PA/VCO/PLL. Basic understanding of high frequency RF theories.

•Experience of using Cadence Virtuoso to review and check chip schematic.

•Proficient in mmWave (60GHz) S parameter measurement by using 100um to 250um probe station.

•Experienced in developing RF calibration code, ATE programing for chip verification by C++.

•Familiar with multi-layer, high speed and high density PCB design and CAD tool operation.

•Knowledgeable of production procedure and requirement.

Working Experience

RF System Engineer at Tensorcom Inc. San Diego 08/2016 present

•Characterize 60GHz Soc Receiver AGC. Play trade off between NF and linearity to minimize PER.

•Measure EVM for TX and RX system with Agilent decoding software. Adjust IQ, LO leakage, phase

noise to improve the EVM.

•mmWave probing test. Evaluate S parameter for TL, PA, Yagi and Patch antenna with 60GHz network

analyzer. Impedance matching calculation with smith chart.

•Engineering board schematic design. Source components and provide guideline for PCB layout.

•Components reduction and performance improvement for the production prototype. Yield rate evaluation

based on assembling procedure and chip process. Estimate product cost and risk.

•Work closely with overseas contracted manufacturer to increase yield rate. Monitor and resolve

problems in assembling process.

•Prepared and delivered demo samples for customers. Provide customer support in timely manner. Debug

product comprehensively both board and chip level.

RF Test Engineer at Tensorcom Inc. San Diego 03/2014 08/2016

•VCO stability test over control voltage, temperature and chip process variation.

•Test chip bring up. Create scripts for PMU, tx and rx synthesizer. Modify chip power up sequence.

Arrange user interface for Chip SPI registers based on system structure.

•Develop scripts for RF ATE in C++. Control test equipment such as the Spectrum Analyzer, Signal

Generator and Temperature Chamber. Analyze the test result and prepare evaluation documents.

•Silicon verification before tape out. Check the chip schematic and layout. Extract the pin information

from chip layout and design BGA module layout.

•Develop Calibration code for three test chips: LDO cal, PLL cal, RX dc cal.

•Failure analysis by taking thermal image for entire Soc.

•Evaluate test equipment and development test proposal for the new mmWave SoC feature.

•Verify firmware with real data transfer. Work with software group to improve the system stability.

Provide hardware support for protocol test, plugfest and Wigig Certification test.

Test Engineer Internship at Tensorcom Inc. San Diego. 09/2013 03/2014

•Evaluate crystal PPM under temperature. Pick up the crystal within ppm requirement to do SMT.

•Measure phase noise on rfpll and refpll. Adjust the loop filter to improve the phase noise of rfpll.

•Measure EIRP for the chip and plot antenna pattern vs beamforming sectors.

•Measure the dc offset of chip with Oscillate Scope. Adjust the three stages PGA DC to minimize the

pga3 output dc offset.

Education

University of California, San Diego, MS Electrical Engineering, Electronic Circuits and System 09/2012 04/2014

Shanghai Jiao Tong University, BS Electrical and Computer Engineering 09/2008 08/2012

Software and tools

C++, Cadence Virtuoso, Altium Designer, VNA, Spectrum analyzer, Oscilloscope, ADS, Matlab, P-spice.

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