TIENG D. NGUYEN (US Citizen)

*** *********** ****, *********, **. 08078 Cell: 856-***-**** ac3d05@r.postjobfree.com PRINCIPAL HARDWARE/FPGA ENGINEER

Project Leadership / Task Management / FPGA / Ultra High Speed Board Design / Low Power Wearable Design CAREER SUMMARY

A highly accomplished Engineering Professional with a proven ability to manage all phases of hardware design, development, implementation and cost reduction. An energetic self-starter with extensive technical, project leadership and supervisory experience. Highly adept with leading edge electronic/logic designs (10+Gbps), re-configurable hardware algorithms in FPGA, testing, and integration towards applications in network computing and data center server to ensure projects are finished on time and at an optimal cost. Areas of experience include:

Advised Intel customers to design in with an Intel super low power wearable AtlasPeak1 Curie SoC that consumes 200uA in a sleep mode for consumer product applications. Recommended the customers to change their design, layout, routing and PCB stackup to have a successful bring up their designs on the first time. Also, screened BOMs of the customer designs for low BOM cost and short lead time for a high volume production.

Helped Titan Medical Inc company to bring up its SPORT flagship, a non-intrusive surgical robotic machine used in hospital operating room, to its final production stage by redesigning the Workstation IO board (WSIOB). The instrument had three separated subsystems. They were a work station unit, central unit and insertion tube unit. They were designed with isolations of 2-MOOP and 2-MOPP per IEC-60601-x standard.

Video server and video storage hardware experience consisted of designing custom video ASICs based on MPEG compression algorithms and video migration from lowest (slowest) to highest (fastest) memory hierarchy. The video ASICs were formed a SIMD systolic array of processors and IO communication channels that provided a fault tolerance with/without performance degradation. The system applications were very flexible and highlighted here for an illustration: video simulation and editing, MPEG encoder/decoder, Video-On-Demand, Terrain Rendering and Volume Visualization, Synthetic Aperture Radar processing applications.

FPGA experience included Xilinx Virtex, Altera Cyclone, and Lattice using Verilog and VHDL languages, ModelSim, NC- Sim and System Verilog Assertion tools for simulation, debug using ChipScope, oscilloscope and logic analyzers. Some highlights of FPGA designs were a memory management unit (MMU) that translated a logical to physical address and generated a page fault, a specialized frame relay processor, Fibre Channel link processor, SONET Virtual Concatenation, interconnect system bus controllers, performance and statistic controllers, DSPs, and glue logics.

PCB experience included incorporation of large multiple pin count FPGAs, CPU (Motorola/Intel/PowerPC/ARM) complex, external memories (RLDRAM/DDR2/DDR3) and discrete logics on high speed board designs using Allegro schematics capture, Hyperlinx for signal integrity and Ansys HFSS for ultra high speed trace (10Gbps and above) geometry structure simulation.

Signal integrity experience included trace geometry constructions. For ultra high speed signals, traces are constructed in differential co-planar microwave structures with embedded coupling capacitors on differential signals. Verified the structures with a S-parameter measurements of two port microwave trace structures. Determined a system channel loss budget in dB.

PCB fabrication experience included lowest cost bare boards by fitting perfecly multiple PCBs on a panel, layer symmetry and copper balance; excellent signal integrity by defining trace geometry and PCB stack up for a control impedance; low coupling noises by runing traces, North-South and East-West, lowest separation rules and maintaining a continous ground return current plane; high quality PCBs by embedding a test coupon that was not only to verify the control impedance but also ensure multiple EMS suppliers to meet the same criteria; design producibility by providing rule sets for trace geometries, minimum separation, grouping, and length matching.

Power distribution experience included a system power design, connector and power plane impedance evaluation, single phase DC converter designs and breadboarded multi-phase DC converter designs, using Bode gain/phase margins for a stability analysis.

EMI/EMC experience included design compliance, test and fix a radiation emission, conducted emission, and ESD on- contact and over-air testings.

Developed test methodology and test verification plan metrics for verifying hardware/fpga designs.

Completed many design turns using Fujitsu’s rigid Hardware Design Life Cycle and FPGA Design Life Cycle processes. The processes were not only ensured high quality designs but also emphasized on DFT, DFM, DFA and design reliability.

Experienced in leading hardware projects with five engineers. PROFESSIONAL EXPERIENCE

Intel Corporation, Santa Clara, CA 10/2016 – Present Lead Hardware Pre/Post Silicon Validation Engineer

* Advised Intel customers to design in with an Intel super low power wearable AtlasPeak1 Curie SoC that consumes 200uA in a sleep mode for consumer product applications.

* Reviewed customers’ schematics and recommended design changes for a proper interface to Intel Curie as such a proper power sequence, ADC power supplies, ADC reference voltage requirements, Bluetooth matching circuit, control USB interface transient voltage issues, reset and boot up strategies for a successful power on cycle.

* Reviewed layouts of critical Bluetooth matching circuits for a proper placement of the matching components, routing traces of interconnected matching components, routing of the antenna feeder trace and antenna trace.

* Recommended PCB layer stackup to provide a 50 ohm transmission line impedance characteristics of the antenna feeder and antenna itself.

* Recommended how to interface with Curie’s internal gyroscope 6-axis sensors, a battery charger, voltage regulators, 1.8V LDO, a dual voltage switching regulators (1.8V/3.3V), and high power switching regulator controllers. The Curie also has interfaces to wireless charger, GPS, NFC & security, HARPTIC sensors, Temperature & Humidity sensors.

* Screened a design BOM for a high volume, short lead time and low cost components.

* Performed internal reviews and recommendations for a high performance and densely integration of a second generation AtlasPeak2 on signal integrity, power integrity, component placement, layout, routing 2.4GHz RF Bluetooth circuits and antenna.

Plexus Corporation, Raleigh, NC 3/2016 – 8/2016

Hardware/FPGA Engineer Consultant

* Analyzed current problems and proposed then implemented solutions to the interconnected interfaces on a Workstation IO board (WSIOB) in a Workstation unit of multi-functional units (Workstation, Patient Cart and Central units) of the robotic non-intrusive surgical machine, SPORT. The WSIOB have a Cortex M0 micro controller with a builtin 1MB memory and 256KB flash memory runs at 120MHz clock. The Cortex M0 controlled three I2C slaves and two I2C expanders to control various IO operations as well as performing an emergency stop if an emergency event occurred. The design was captured in Altium schematics capture tools.

* Re-designed two DC/DC converters using MatLab/Multilink to provide adaquate electrical current for the WSIOB operations and eliminated one large transformer by moving a power on button to different isolation barrier.

* Re-designed the WSIOB layer stackup, routing and power distribution to pass EMC/UL compliance.

* Re-designed an emergency stop circuit (E-STOP) in CPLD using XC9572 and Xilinx Vivado tools.

* Enhanced the WSIOB circuits to provide isolations for 2-MOPP and 2-MOOP protections per IEC-60601-x standard.

* Performed a risk management (DFMEA) on the workstation unit.

* Modified board placement, CAN bus connectivity, connectors and cables to meet DFX design goals. Fujitsu Network Communi, Pearl River, NY 10/2002 – 2/2016 Principal Hardware/FPGA Engineer

Summary of work at FNC included architecture and design of various embedded processor (PowerPC/ARM/PSoC) boards, power distribution, power sequencing and reset strategies, signal integrity, PCB layer stackup and layout. Some designs had a mix mode as in ROADM design. For a board design framework, a rigid Fujitsu hardware life cycle process that started from a concept to a production was followed for design documents, DFM (components and connectors packages, board profile and copper pattern), and DFT (configurable JTAG chain), test plan metrics and verification, prototype debug and bring-up, also assistance of test setups and supports for an in-house manufacture. For a FPGA design, a Fujitsu FPGA/ASIC design process was followed with a good RTL coding practice must have a default CASE statement, a mix of traditional Verilog and System Verilog (UVM) verification. Synopsis tools were for synthesis; errors and warning reports were scanned with Perl scripts; PAR tools were Quartus II and Xilinx ISE as well as exploring Vivado. Experiences at FNC were below.

* Helped customers to troubleshooting systems down to circuit levels. Suggested workaround the issues until software and/or hardware fixes were delivered.

* Designed/analyzed a new EPON design project that has 8x10G clients interfaces and 2x40G netwok interfaces using Broadcom ARAD and Pioneer chips. Employed ANSYS HFSS to design 10Ghz pre layout traces with specific routing patterns, trace width, trace high and trace surface roughness, trace length matching, and mix dielectric constants of multilayer stackup.

* Designed a 24-layer PCB 8-Degree ROADM board in FW9500 using Allego 16.5 schematics capture and constraint tools. Designed, debugged and brought up the 8-Degree optical switch board with 88 channels at 40Ghz each in a single fiber. The optical switch board consisted of a WSS (Finisar/JDSU), an OCM (Axsun/Photop), 1x4 optical switch and supporting electronics for optical power monitor. An ARM processor in 1152-pin Altera SoC Cyclone 5 performed a system performance and diagnostics. The Cyclone 5’s ARM processor interfaced to an external DDR3 which stored a runtime controlled program after loaded from a compressed bootrap reset routine in its flash memory. The design was supported a configurable JTAG chain, DFM, and DFT at board and system level test documents.

* Took parts in creating a new FW CDS product and then designed, debugged and brought up a storage and fan subsystem. The fan system was a high voltage (-48V) analog and digital I/Os designed on a 16-layer PCB using Allegro 16.5 schematics capture tool. The fan subsystem was employed a Cypress PSoC, a micro-controller, to regulate fan speed based on a sensed ambient temperature. Wrote a C-code controlled firmware on the Cypress PSoC Designer tool to compile and download to internal PSoC flash memory. The firmware was a self booting, reporting interrupt events and diagnosing its health. The design was supported a configurable JTAG chain, DFM, and DFT at board and system level test documents. I also coded a RTL for a system communication bus in Verilog, synthesized in Synopsis, and mixed traditional verilog and SystemVerilog verifications. Wrote a test plan metrics, scoreboard, for use against the verification process. Responsible to debug and bring up the FPGAs in the lab.

* Performed Xilinx Virtex 6 FPGA designs for FW9500 PIUs as such OUPSR (optical unidirectional path signal redundancy) and MUX-sponder. The FPGAs performed a network management and control datapath facility. RTL was coded in Verilog, synthesized in Synopsis, and mixed traditional verilog and SystemVerilog verifications. Wrote a test plan metrics, scoreboard, for use cases against the verification process. Responsible to debug and bring up the FPGAs in the lab.

* Worked on cost reductions on various existing designs in FW9500 and FW4100ES ESLANSU for a high return on investment (ROI) with high denser FPGAs and lower layer PCB stack up for a reduce cost. The design was supported a configurable JTAG chain, DFM, and DFT at board and system level test documents. While FPGAs were re-compiled with added emulation circuits to allow an unchanged software still saw the same old behavior on a new hardware.

* Brought in a Fibre Channel transport expertise to Fujitsu Network Comm (FNC) product portfolio. Led the efforts to define and architected board level and FPGA level design to transport a Fibre Channel (FC) protocol over various distances, 1K and 8K mile links. Helped system engineers to define feature sets of FC requirements and trained design engineers on FC aspects. Then led, designed, debugged and brought up the FW4100 1G/2Gbps SANSU (storage area network service unit) design with five other subordinate engineers. The SANSU design was implemented on a 32-layer PCB with impedance control for 50 ohm transmission line and 100 ohm differential lines. Also, designed -48V power bus for point of load (POL) DC/DC converters which stepped down to 5V, 3.3V, 1.5V, 1.2V, 1.1V and 0.75V to power the SANSU board. The design was supported a configurable JTAG chain, DFn at board and system level test documents. Coded a critical verilog blocks on a clock adaptation FIFOs and flow control. Verified them in traditional Verilog test bench and ModelSim.

* Provided a backend support of a full hardware life cycle process of the design included writing a board description spec

(HUDS), board level engineering test spec (HDVS), manufacturing board level test spec (N-spec) and manufacturing system level test spec (MSTS). Wrote menu driven C-functions to test the board during a hardware debug cycle and documented them in the N-Spec for a manufacturing test technician to test production boards.

* Maintained and tracked provisions in a design through a propreitary revision control (PIMS), problem reports in Oracle problem tracking report (PTR) and engineer change notice (ECN).

* Following tools were used in Fujitsu designs: Synplify, Modeltech, Xilinx, Altera, Lattice, Verilint, Synopsis, Allegro, Hspice, ADS signal integrity tools. For a very high speed signal from 10+Gbps, an ANSYS HFSS tool was used to simulate a trace geometries, PCB layer stack up, mixed dielectric constants, and specific routing pattern to ensure channel losses within a channel loss budget.

* Led hardware projects with four to five hardware engineers. David Sarnoff Research Center, Princeton, NJ 9/1995 - 10/2002 Staff Hardware Engineer

Summary of work at David Sarnoff Research Center included architecture and design of Intel 486 processor video switch board, CPU board with proprietary Video ASIC processors in a SIMD architecture, power distribution utilized thick copper layers and LDO converters, reset strategies, signal integrity, power distribution, PCB layer stackup and layout. Simulated Video processors and IOs and performed a static timing analysis of the processor and IO chips. Experiences included in below.

* Designed and maintained a complete end-to-end RF/HFC coax cable network for a Video-on-Demand (VOD) in a cable TV environments.

* Investigated a low yield of cutting edge high pin count ball grid array FPGAs on PCB and documented the improved design process into a standard procedure for a next project.

* Designed a 24-layer PCB and architected a proprietary multi-gigabit (1.25GHz and 2.125GHz Fiber Channel/ Gigabit Ethernet physical layer) video switch for the second generation VOD server using 500K gate Altera 10K200E with 672 pin BGA as a target device. Design included virtual output queue (VOQ) DPRAM to output data to VSC870 transceiver, external FIFO interface for retrieving packets from the VSC870, a CAM routing table lookup, a ping messaging controller broadcasts its health status and monitors other boards’ health, and CRC generation/checking. Several embedded dual- clock buffers were used for transferring packets between the multiple clock domains, 125MHz, 66MHz, and 31.125MHz. Verification included a multi-board environment used for transferring test packets through the Vitesse VSC880 switch model in VHDL.

* In the second generation of the video-on-demand server, I created, simulated and measured a High Speed PCB with 24- layer and 50 ohm control impedance, High Frequency Signal Routing, Power Distribution, Single and Differential terminations, length matching, and crosstalk budgeting rules for all signal frequencies, up to 2.125GHz,. Was a mentor to junior engineers on the signal integrity subject.

* Designed memory modules for a SIMD (parallel) processor board with 128 processors for a video simulation, MPEG encoder, VOD, Terrain Rendering and Volume Visualization, Synthetic Aperture Radar processing applications.

* Designed system clocks (using PLL technology) with a 2ns clock jitter throughout the system, distributed in phase 84MHz, 42MHZ, and 21MHZ to synchronize a massively array processors and IO modules. Used HSPICE to simulate a clock tree distribution transmission line on backplane and plugged-in-boards for LSI Logic sea of gate ASIC chip.

* Designed and extracted ALU unit’s worst case static timing and

* Specified the processor and IO external interface timings after extracting and analyzing the Processor and IO ASIC pin worst case delay paths.

* Verified functionalities of the array element Processor and IO ASICs using LSI sea of gates CMD design tools.

* Ran HSPICE circuit simulator to verify sea of gate IO buffer capable to drive a loaded transmission line on a PCB for LSI Logic sea of gate ASIC technology and recommended a characterized IO buffer for use in the design. Eastern Research, Inc., Moorestown, NJ 2/1994 - 9/1995 Design Consultant Engineer

* Designed a voice call connection request processing for SS7 signaling system was based on Bell Core GR303. The call processing agent ran on 8 T1/E1 lines with an embedded MC68360 processor. The design was used Xilinx XC4010 to process 2048 On/Off Hook signals on 8 T1/E1 lines. The processed On/Off Hook signals were put on FIFO for a higher level processing. Xilinx XACT tools were used for the FPGA development.

* Designed a high reliable derived Stratum 3 clock. The design had to meet stratum 3 requirements included BellCore 378 and 1244. The design was based on redundant clock modules constantly locked in phase with an incoming stratum 3 clock. When the incoming stratum 3 clock ceased, an online clock module maintained its derived clock for up to 24 hours and less than 3ppm drift. If the online clock module failed, an offline clock module took over. The high reliable PLL design consisted of phase counter, phase error, phase/frequency detector, clock fail detector, clock switchover, and control circuits all in XC4010. Xilinx XACT tools were used for the FPGA development. Gandalf Data Ltd/Infotron System Corp., Cherry Hill, NJ 8/1986 - 1/1994 Principal Engineer

Summary of work at Gandalf/Infotron System included architecture and design of Motorola MC68020 processor frame relay board with a custom frame relay co-processor implemented in XC4005E, power distribution utilized thick copper layers and LDO converters, reset strategies, signal integrity and PCB layer stackup. Wrote a Pascal algorithm to simulate a system behavior of a patented QUIC bus in term of system packet memory requirements.

* Designed a 12-layer PCB and architected an embedded Motorola MC68020 frame relay interface module that employed a company proprietary cell relay switching technology. The core of the project was designed a custom RISC in Xilinx FPGAs with an ALU and Instruction execution units, debugged, and wrote code for the custom RISC processor. The RISC processor consisted of Xilinx XC4005E and XC3090 at 25MHZ and an external sequential microcode memory. The custom RISC processor examined, processed frame headers, stored and forwarded frames to/from the physical link interface. The module performed 2048 PVC connections and processed 12,000 frames/s. The simulation environment was based on Mentor Graphic QuickSim version 8.1.

* Analyzed IO buffer memory requirement for the patented 1.2Gbps switching QUIC bus interface by writing a network simulator in Pascal for exploring system variables such as packet sizes, number of packets, and packet transit delay throughout the system.

* A group leader in charge of two enhanced embedded products to higher performance at a lower cost on 10-layer PCBs. One was an dual link statistical multiplexer from 19.2Kbps to 64Kbps. A second project was enhanced the current multiplexer to be compatible with AT&T subrate data multiplexer. Managed one-hardware and two-software engineers. Both projects were capable to carry mixed voice and data channel to PBX systems. AT&T Information System., Middletown, NJ 8/1985 - 8/1986 Technical Staff

* Designed a 12-layer PCB and debugged a VME processor module with a 10 MHZ Motorola 68010 and a zero-wait-state external discrete memory management unit (MMU) to run the system 5 UNIX operating system. The processor module was the main element in the AT&T Network Protocol Processor (NPP) product. Burroughs Corp., Paoli, PA 9/1981 - 8/1985

Engineer

* Designed logic gates, spice simulation, and layout of a chemical sensor processing CMOS chip. The project was designed with a dynamic CMOS circuit for the VLSI design graduate course work at University of Pennsylvania.

* Received an award in generating a computer algorithm in Algo language to create and verify a PROM based state machine for in house use. The design saved company many months of MI state machine redesign. COMPUTER SKILLS:

Hardware: PC, SUN Sparc, SGI

O/S: UNIX, Linux, and Windows

Languages: Parallel C, C/C++, Pascal, LISP, Fortran, VHDL, Verilog, System Verilog, IBIS, X86 Assembly. EDA Design Tools: Altium, Cadence, Mentor Graphic, ViewLogic, VeriBest, Examplar, Synplicity, Aldec, ModelSim, Xilinx Foundation, Altera Qartus, LSI CMDE, AT&T ASIC tools, Ansoft 3-D, AMPspice2.5D, HyperLynx 2-D signal integrity, Ansys SI and HFSS. Analysis Tools: MATLab/Simulink, MS Excel, Project, Visio, Chronology Timing Desinger. Office Tools: MS Office (Word, PowerPoint, Access, Project), FrameMaker, Acrobat writer Vendors: OrCAD, Innoveda Viewlogic, Mentor Graphics Board Station, Synplicity, Synopsis, Avanti! (H-Spice), AMP, Cadence

TECHNOLOGY EXPERIENCE:

LAB Tools: In-circuit Emulators, In-circuit debugger/monitor, cPCI Bus analyzer, HP Logic analyzers, oscilloscopes, Bit Error Rate Testers, Gigabit Ethernet traffic generator/checker SmartBit, Function generators, Burn-in oven, RF power measurement equipment, lasers, optical sources / power meters, and optical attenuators.

SIGNAL INTEGRITY: HP 8510 Spectrum analyzer, Tektronic 11801C TDR, Agilent VNA Communication signal analyzer, LeCroy LC584AL digital scope with jitter measurement, Avanti Hspice, AMP spice, and HyperLynx, Cadence ADS and ANSYS HFSS, Bode 100, and LeCroy SPARQ-4000e. Devices: Xilinx Virtex and Altera Cyclone 5 FPGA, Gate Array and standard cell ASICs, SDRAM, LVDS, ECL, PECL, CMOS, GTL, HSTL, SSTL, and TTL discrete logic SRAM, CAM, Dual-Port, FIFO, Flash, EPROM, AMD, Lattice, Cypress PLDs, MC68XXX, X86, PowerPC860, Cypress PSoC, Vitesse VSC870, VSC880, Silicon Labs PLL and timing devices, Broadcom ARAD and Pioneer, and DDR3. Standards: cPCI, USB2.0, I2C, RS232, RS485, X.25, HDLC, TCP/IP, PCIe, SATA, Fibre Channel (SAN), MPEG-1, MPEG-2, RAID, T1/T3, ATM, SONET, OTN, CPRI (Cellular network interface). EDUCATION:

BSEE Drexel University, 1981 Control Theory and Computing MSCS University of Pennsylvania, 1984 Communication and Computational Architecture

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