Roshan Shree Balachandar

**** **** ****** **, *** 3R, Chicago, Illinois, 60607 ac3czn@r.postjobfree.com 312-***-**** github.com/rshree2 www.linkedin.com/in/roshan-shree-balachandar-a3462b9b A self-driven engineer expanding my horizon in the field of ASIC/FPGA/SoC/PCB Design and Verification. EDUCATION

Master of Science/ Electrical and Computer Engineering May’17 University of Illinois, Chicago (UIC), Chicago, IL GPA:3.62/4 Bachelor of Engineering/Electrical and Electronics Engineering May’15 Anna University, Chennai, India GPA:8.0/10

Relevant Coursework: Advanced VLSI Design, Computer Systems Design, Advanced Computer Architecture, Parallel Processing, High Performance IC Systems, Analog and Mixed Signal VLSI, Digital Systems design. TECHNICAL SKILLS

Programming Languages: C/C++, Python, Embedded C, Verilog, SystemVerilog. Operating System: Windows, Linux, macOS

IDE/Tools: Arduino, AVR, MATLAB, Eclipse, LabView, ROS, Cadence Virtuoso, HSpice, ATLANTA-M, KICAD, Altium, Eagle, OrCAD, PSpice, PCB Editor, LTSpice, Xilinx ISE, ModelSim, QT Creator Hardware Platforms: FPGA (Xilinx Spartan 3E, Atrix-7), Microcontrollers (8085, ATMega328, ARM, PIC) ACADEMIC PROJECTS

Frequency Compensation Techniques for Feedback TIA circuits (HSpice, Cadence Design Environment) May’17 Implemented multiple compensation techniques for the given TIA circuit. Analyzed stability for each one of the techniques by simulating its Phase margin and Gain Margin. Achieved increased bandwidth of 20% without compromising performance. Implementation of Dense Parallel algorithms in Clusters (C/C++, UIC Extreme Cluster, MPICH2 tools) Sep ‘16 Developed a parallel Matrix Multiplication code for a hyper cube network of processors present on UIC Extreme High-Performance Cluster which consists of 203 nodes. Analyzed speedup, efficiency, and timing requirements. Low Power Synchronous SRAM with Logical Units (Cadence Design Environment, HSpice) Apr’16 System includes 16x32 SRAM Array, De-MUX, Adder, Read Write operations using 45nm technology. Analysis and design of leakage control techniques to reduce power consumption by 40% and performance increment by 25%. RTL Design and Testbench verification of multiplier datapath (Verilog, Altera Quartus, Modelsim) Dec ‘15 Designed a datapath with components to perform 16 bit add-and-shift Booth multiplication, and a Moore-machine FSM in One hot style to control the datapath of Booth multiplication. The datapath was verified with custom inputs. Achieved 100% accuracy. Design of operational Amplifier (Cadence Design Environment, HSpice) Aug '16 Designed a two-stage amplifier for given specifications. Determined the dimensions of transistors based on theoretical values and tuned the performance of the op-amp to achieve desired performance.

Design verification of an Ethernet Switch (Verilog, System Verilog) Aug’15 Implemented RTL design of a 2x2 ethernet switch in Verilog and verified its functionality by building a test environment using System Verilog. Random Verification was used with the environment comprising of generators, monitor and checker blocks. Real-Time Clock for processor synchronization (KICAD, Altium) Aug’15 Implemented a real-time clock to synchronize the GPU and the processor to prevent timing issues during data transfer-a cheap and an accurate alternative to a more complex software synchronization. RESEARCH WORK

Carbon Nano-tube Sensory Circuit (LTSpice, Altium, ARM, QT Creator, ATMega328p) Aug’17-Present Designed a self-adjustable Carbon Nano-tube (CNT) sensing circuit that detects minor changes in the resistance(milliVolts) when exposed to different gases at various ppm (methane at 10ppm). Achieved an absolute error of <1% in resistance detection. Implemented a dedicated GUI that plots real time data through a serial communication.

Multi-Layer PCB using Voltera Design Suite (Voltera PCB Design Suite) Aug’17-Present Implementing a multi-level PCB separated by resin deposition except the vias to facilitate connection from one layer to the other. Analyzing multiple parameters such as thickness, temperature dependence, heating effects during implementation. CERTIFICATION

LiveWire, Electrical Design Automation (OrCAD, PSpice, PCB Editor, Verilog) May’14 Implemented a dedicated sound card by analyzing the sampling frequency, buffer system, DAC, ADC and output ports. Extensive use of Capture for schematic implementation and PSpice for data, timing analysis, transient and noise parameters. ACHIEVEMENTS

Developed a dedicated logic unit using Finite State Machine for Semi-Automatic Gear (patent in process). Secured the Innovative award for the design of Sign Language translator. Secured the 5th and the 2nd place in Midwestern Robotic Design Contest 2015,2016.