PAVANKUMAR GV

Contact No: +91-827*******

Email: ac3bma@r.postjobfree.com

Career Objective

To develop my career as a VLSI Engineer where I will be a valuable team member, contributing quality ideas and work for an organization where there is an ample scope for individual as well as organization growth in VLSI Design and Develop.

Academic Details

M.Tech in VLSI design and Embedded systems, Dr.Ambedkar institute of technology, Bangalore 67% 2014

BE in Electrical and Electronics and Engineering,

Dr.Thimmaiah institute of technology 50.14% 2012

Work Experience

Currently working as Technical Support Engineer for IBM INFO SERVICE PVT, Bangalore (7nd July. 2016 to till date).

Skills and responsibility

Improve the circuit design methodology and execution.

Troubleshoot, debug and upgrade existing systems.

Experienced in VHDL, Verilog, Xilinx Spartan FPGA programming.

Expertise in Digital Design and Advanced Verification Techniques

Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools.

Knowledgeable in CMOS VLSI design, Verilog RTL coding.

Knowledgeable in ASIC front end/back end design.

Knowledgeable in Physical design flow.

Experience in Simulation, Synthesis, MAP and Place & Route.

Expertise in development of IP Level Verification platform using System Verilog/ Verilog/ VHDL

Problem solving, Team work, Multitasking and I able to work a diverse team environment.

Course & Certification

Internship from Feb-16-July-16, Oracle informatics from IT Quest Solutions, Bangalore.

Undergone Software Testing from IIBC, Bangalore.

2011 GATE exam qualified.

Project Detail

"Time Period Minimization of Circuit Execution in High Level Synthesis" as a part of M.Tech Final year academics."

We have used Retiming Techniques to implement to design circuit, as the circuit complexity increases, circuit consume more area, the designer attracted towards reconfigurable fabrics. In this project we mainly concentrate on area, power and delay. Reconfigurable adder architecture is one of the most efficient and effective in reducing area and delay in circuit execution using algorithms with MATLAB tool.

"CMOS 8 Bit Binary Multiplier"

The main objective of the work is to design for high speed applications, one of the most suitable topologies is Wallace Tree Multiplier. The complexity depends on the logarithm of the input bit count using Micro wind/Xilinx and Advanced Designed System.

" New Low Power Full Adder Cell in CMOS Inverter "

The cell offer less power consumption in comparison with the conventional and current implementation of the full adder cell, especially at low voltages and simulation is improved in terms of power consumption using Micro wind/Xilinx and Advanced Designed System.

" Illumination Design of Underground Mine Model "

This project focus on an industrial lighting is to improve the safety, increase production. And low power consumption of the energy it shows that should benefit the use of lighting that is consistent with the capabilities of modern technology.

Software Proficiency

Programming Language

: Verilog, System Verilog, VHDL

Operating Systems

: LINUX, UBUNTU, WINDOWS

Simulator tools

: Xilinx14.5, Matlab, Microwind, Cadence

VLSI Domain Skills

HDL

:

Verilog

HVL

:

System Verilog

EDA Tool

:

Xilinx ISE

TB Methodology

:

UVM

Domain

:

ASIC/FPGA front-end Design and Verification

Knowledge

Digital design, RTL coding, FSM based design,

Simulation, Code Coverage, Functional Coverage,

Synthesis

Verification Methodologies

:

UVM, constrained random & coverage driven

methodologies

Publications

Title: “Time-Period Minimization of Circuit Execution in High Level Synthesis”

Publisher: International Journal of Advanced Research in Computer Engineering & Technology, (www.ijrcet.in). ISSN: 2278-1323, Volume 3, Issue 7, July 2014.

Title: “Time-Period Minimization of Circuit Execution in High Level Synthesis”

Publisher: Presented on National Conference of Electrical & Electronics Engineering

(ID: NC3E:451) NCEEE - 2014 on 5th June 2014 at HKBK Institute of Technology, Bangalore.

Industrial Exposure

Industry visit: Deportment of Space Indian Space Research Organisation Master Control Facility (MFC), Hassan.

Internship: IT Quest Solutions, Bangalore.

Language

Kannada

English

Telugu

Hindi

Strength & Hobbies

•Work effectively with diverse group of people

•Adapt very quickly to new environments

•Self-motivated and motivate others

•Quick learning

•Listening music

•Playing cricket

Personal Address

Permanent Address

:

S/o Gadhi Venkataramaiah, H Bypanahalli Village, Hebbni Post, Byrkoor Hobli, Mulbagal Taluk, Kolar District, Karnataka – 563131

Languages known

:

English, Kannada, Telugu and Hindi.

Date of Birth

:

July 10th 1985.

Gender

:

Male.

Mobile

:

+91-827*******

Email

:

ac3bma@r.postjobfree.com

Declaration

I hereby declare that the above information furnished by me is true and correct to the best of my knowledge and belief.

(Pavankumar G V)

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