Peter F. Lindberg
Plymouth, MN 55442
Mobile 763-***-****
ac3azz@r.postjobfree.com
WORK EXPERIENCE:
Starkey Hearing Technologies 12/16 – 11/17
Principal IC Design Engineer Eden Prairie, MN
Responsible for all timing closure activities on their 40nm ultra low power ASIC
Synopsys flow: DC-Graphical for RTL synthesis, ICC Place & Route, ICV, and PrimeTime/SI/PTPX for STA and Power estimation
LSI/LSI Corporation/Avago Technologies/Broadcom 11/99 – 11/16
Principal Customer Design Engineer Mendota Heights, MN
Extensive use of PrimeTime, PrimeTime-GCA, Design Compiler, Design Compiler-Topographical and ICC to close timing with 65nm and 28nm ASIC technology
Several years of experience on complex low power 28nm designs that utilize UPF to define multiple power domains running at different voltages
Recognized PrimeTime STA and timing closure specialist for BroadCom
Timing constraint generation/debug for customer and BroadCom IP constraints
Hold several patents related to timing closure scripts
SNUG award winner for paper on how PrimeTime-GCA speeds up timing closure
Staff Advanced Design Analysis/Modeling Engineer Houston, TX
Timing closure on 90nm SAS Expander chip
Performed PT-SI signoff STA and constraint debug on several 90nm SAS RAID-on-Chip(ROC) chips
Staff SAS ROC Design Engineer Houston, TX
Synthesized verilog RTL with Design Compiler and STA with PrimeTime for 90nm SAS 2.0 ROC chips
Wrote and debugged verilog simulation regression tests
Ran Equivalency checking on RTL (Cadence Conformal and Synopsys Formality)
Worked with third party IP vendors to make their RTL more timing closure friendly
Staff ASIC Design Closure Engineer Bloomington, MN
Specialized skills in SoC static timing analysis, design planning, logical/physical optimization, and IP timing models
Assisted in timing closure on several ASIC designs greater than 10M gates with large quantities of clock domains, soft/firm/hard IP, and many types of memories
Extensive work with timing driven placement/routing/physical synthesis/optimization tools including LSI’s proprietary MPS, MRS, Synopsys Physical Compiler, Synplicity AmplifyRapidChip, Synopsys(Avanti) Jupiter/Apollo/Astro/Saturn/Milkyway
Working with various EDA vendors (Synopsys, Magma, Synplicity, Cadence, etc.) to improve quality of tools and evaluate potential tools to add to FlexStream (build vs. buy)
Working with LSI IP groups (CoreWare groups) and external IP vendors to model timing of IP and ensure smooth implementation into FlexStream, RapidWorx
Develop and maintain several proprietary tools (written in Python, Perl, Tcl, C++) for FlexStream and RapidWorx
Honeywell SSEC 1/93 – 10/99
Design Automation/Customer Design Engineer Plymouth, MN
Assisted customers in using SSEC’s ASIC design flow to ensure first-pass success, from RTL netlist synthesis through static-timing and simulation to test
Served as interface between customers and engineers for SSEC’s 1M+ gate HX3000 technology
Made several customer presentations for the HX3000 technology
Developed and maintained software, written in C and PASCAL, for the VLSI Design System(VDS) toolkits
Support marketing and program managers in sales pitches and VDS toolkit questions
Transistor level design of SSI components
Worked three months in Florida helping customers use the VDS toolkit and helping translate an existing microprocessor design into Honeywell technology
Design and implementation of regression tests for VDS toolkit software using configuration management tools
EDUCATION:
Bachelor of Science in Electrical Engineering, University of Minnesota, June 1995
Completed several graduate level courses in VLSI design at the U of M – Twin Cities
REFERENCES:
Available upon request