Engineering Manager
Resume:
JOSEPH TZOU RESUME OF QUALIFICATIONS
HOME ADDRESS
Mountain View, CA 94040
Home Phone: 650-***-****
Cell Phone: 650-***-****
e-mail address: **********@*****.***
EDUCATION:
Ph.D. in Physics, May 1983 Univ. of Illinois, Urbana, IL
M.S. in Physics, October 1978 Univ. of Illinois, Urbana, IL
B.S. in Physics, June 1976 Tsing Hua Univ, Taiwan, Rep. of China
WORK EXPERIENCE:
Senior Member of Technical Staff May 2005 – September 2015
Director of Design Engineering March 2000 – May 2005
Cypress Semiconductor, San Jose CA
- In charge of SRAM Design Center in San Jose. Products include Wide IO QDR, QDR4, QDR2+/QDR2, QDR1, Synchronous SRAM/NoBL, low power SRAM (MoBL), fast Asynchronous SRAM, and 18M 1T cache RAM. Process used include 13nm - 0.25micron CMOS technology.
- First in the world to deliver the following products: 1.2GHz 288M QDR4, 550MHz 144M QDR2+, 400MHz 144M QDR2, and 250MHz 72M SSRAM/NoBL.
- Major circuit blocks used in QDR4 include PLL, high speed HSTL IO, programmable BIST, Voltage regulator, ECC, multiple memory bank structure to support two operations (Read or write) at the same time, CAM for late write addresses, read FIFO at IO for latency options, write FIFO at memory for late write data, JTAG, parallel interface for test modes, e-fuse, synchronization between various clocks.
- Granted 17 US patents related to circuit design.
- Gross profit margin exceeds 58% from the products designed by my team.
- Debug all SRAM products designed in San Jose. Write all engineering characterization programs for all products designed in San Jose.
V.P. of Engineering October, 1998 – March 2000
SRAM Senior Director May, 1995 – October 1998
SRAM Design Manager September, 1994 - May, 1995
Galvantech Inc., San Jose CA
- V.P of Engineering for 1 and 1/2 years. Responsibilities include Design, Product, and Test Eengineering for SRAM. Products include 18M SSRAM/NoBL, 9M NetRAM/Dual Port, 1M Dual Port, and 4M/3M/2M/1M Asynchronous SRAM.
- In charge of backend operations for 2 years. Responsibilities include Test and Product engineering, test and assembly vendor interface, QA/QC, production control, and MIS system. Achieved $13.5M per quarter revenue and $5.5M profit in Q3 ’97 before moving back to design engineering.
- Supervising synchronous SRAM design. Interfacing with wafer foundries in Taiwan and U.S.
Director, Device Physics & Product Analysis October, 1990 - September, 1994
Manager August, 1989 - October, 1990
Supervisor December, 1987 - August, 1989
Senior Device Physicist February, 1987 - December, 1987
Paradigm Technology, San Jose CA
- Managing Synchronous SRAM product line including product, test, quality/reliability engineering. Products include 64Kx18, 32Kx36, 32Kx18, 32Kx9 burst SRAM, 128Kx9 synchronous SRAM, and 1Kx18, 4Kx18 FIFO.
- Managing circuit and layout design groups for 6 months. Products taped out include 64Kx18, 32Kx36 burst SRAM and 128Kx8 SRAM.
- Yield enhancement and failure analysis (including wafer SORT, burn in, and lifetest) for all SRAM products. Manage the software engineers to write programs for Laser repair and defect analysis.
- Develop CMOS technologies for 4M SRAM (with TFT, W-plug, etc.) and 256K and 1M SRAM (with load resistor). Develop self aligned processes to minize the cell size.
- Hold 7 US patents on the SRAM cells and self-aligned process.
- Design and layout the core cells, test patterns, and process monitors for CMOS technologies.
- Set up automatic testing and analysis system for process evaluation, device modeling, and wafer level reliability studies. Write modeling parameter extraction programs for SPICE simulation. Set up TVS measurement system to monitor mobile ion concentration. In charge of the electrical test and trend charts for SPC (Statistical Process Control).
-. In charge of the design rules for 256K and 1M SRAM technologies.
Member of Technical Staff July, 1984 - February, 1987
Senior Engineer July, 1983 - July, 1984
Advanced Micro Devices, Sunnyvale, CA
- Project leader to study the reliability of CMOS VLSI. The failure mechanisms studied include hot electron injection, oxide breakdown, soft error, hydrogenation of the poly silicon, electromigration, ESD, and CMOS latch up.
- Project leader to study the low temperature CMOS VLSI.
- Project leader of the device modelling and IC yield analysis.
- Develop CMOS technologies for 64K, 256K, and 1M SRAM.
- Set up automatic data acquisition system for device characterization, modelling, and reliability study.
- Design test structures for CMOS technologies.
- Monitor and evaluate a university project supported by SRC.
Adjunct Lecturer September, 1984 – August 1995
Department of Electrical Engineering
University of Santa Clara, Santa Clara, CA
Teaching graduate courses on semiconductor physics, device physics, and Si-SiO2 interface. Codirector of a short course on "Thin Dielectrics for VLSI-Physics and Technology."
PUBLICATIONS
1. "Generation Annealing Kinetics of Interface States on Oxidized Silicon Activated by 10.2 eV Photo-Hole Injection" J. Appl. Phys. 53, P.8886 (1982)
2. "Effects of Avalanche Injection Currents on the Endurance of Si MOS Devices" 1982 IEDM Technical Digest P.753
3. "Generation Annealing Kinetics and Atomic Models of a Compensating Donor in the Surface Space Charge Layer of Oxidized Silicon" J. Appl. Phys. 54, P.944 (1983)
4. "Endurance of Si MOS Devices" Proc. 1983 Int. Sym. on VLSI-TSA, Taipei, Taiwan, Rep. of China, P.174
5. "Generation-Annealing Kinetics of the Interface States at 0.25 eV above the Midgap and the Turn-Around Phenomenon on Oxidized Silicon during Avalanche Electron Injection" J. Appl. Phys. 54, P.2547 (1983)
6. "Deactivation of the Boron Acceptor in Silicon By Hydrogen" Appl. Phys. Lett. 43, P.204 (1983)
7. "Effects of KeV Electron Irradiation on the Avalanche-Electron Generation Rates of Three Donors on Oxidized Silicon" J. Appl. Phys. 54, P.4378 (1983)
8. "A study of the Atomic Models of Three Donorlike Traps on Oxidized Silicon with Aluminum Gate from Their Processing Dependencies" J. Appl. Phys. 54, P.5864 (1983)
9. "Field Dependence of Two Large Hole Capture-Sections in Thermal Oxide on Silicon" Appl. Phys. Lett. 43, P861 (1983)
10. "Deactivation of Group III Acceptors in Silicon During KeV Electron Irradiation" Appl. Phys. Lett. 43, P.962 (1983)
11. "Effects of KeV Electron Irradiation on Optical Generation of Hole Traps in Thermal Oxide on Silicon" J. Appl. Phys. 55, P.846 (1984)
12. "Study of the Atomic Models on Three Donorlike Defects in Si MOS Structures from Their Gate Material Dependencies" J. Appl. Phys. 55, P.1525 (1984)
13. "Some CMOS Device Constraints at Low Temperatures" IEEE Elect. Dev. Lett. EDL-6, P.33 (1985)
14. "The Temperature Dependence of Threshold Voltages in Submicrometer CMOS" IEEE Elect. Dev. Lett. EDL-6, P.250 (1985)
15. "Process Dependence of Hot Electron Injection in MOSFET's" P.359, Proc. 3rd Int. Sym. on VLSI Science and Technology. Toronto, Canada, 1985
16. "Hot-Electron-Induced MOSFET Degradation at Low Temperatures" IEEE Elect. Dev. Lett. EDL-6, P.450 (1985)
17. "Hot-Carrier-Induced Degradation in p-channel LDD MOSFET's" IEEE Elect. Dev. Lett. EDL-7, P.5 (1986)
18. "Temperature Dependence of Latch-up Characteristics in LDD CMOS Devices" IEEE Elect. Dev. Lett. EDL-7, P.92 (1986)
19. "Temperature Dependence of CMOS Device Reliability" Proc 1986 Int. Reliability Physics Symposium, P.175
20. "Comparative Study of NVM Structures" 1986 Int. Conf. on Semiconductor and Integrated Circuit Technology P.491
21. "The Reliability of CMOS VLSI" 1986 Int. Conf. on Semiconductor and Integrated Circuit Technology P.641
22. "A CMOS Technology for Fast 256K Static RAM" 1986 Int. Conf. on Semiconductor and Integrated Circuit Technology P.427
23. "Temperature Dependence of Charge Generation and Breakdown in SiO2" IEEE Elect. Dev. Lett. EDL-7, 446 (1986)
24. "The Effects of the LDD Structure on the CMOS VLSI Utilizing the Oxide-Spacer Technique" ECS meeting, San Diego, CA, October, 1986
25. "Charge Generation and Breakdown in SiO2" ECS meeting, San Diego, CA, October, 1986
26. "A High-Performance CMOS Technology for Very Fast Static RAM's" 1986 IEDM P.600
27. "Structure and Frequency Dependence of Hot-Carrier-Induced Degradation in CMOS VLSI" Proc. 1987 Int. Reliability Physics Symposium P.195
28. "An Advanced CMOS Technology with Novel Bipolar Transistors" ECS meeting, Philadephia, PA, May 1987
29. "Hot-Carrier-Induced Latchup and Trapping/Detrapping Phenomena" 1989 Int Reliability Physics Symposium P.110
US PATENTS
Patent number Title
1 9,666,255 Acess methods and circuits for memory devices with multiple banks
2 9,640,237 Acess methods and circuits for memory devices with multiple channels and banks
3 8,873,264 Data forwarding circuits and methods for memory devices with write latency
4 8,705,310 Access methods and circuits for memory devices having multiple banks
5 8,527,802 Memory device data latency circuits and methods
6 8,358,557 Memory device and method
7 8,149,643 Memory device and method
8 8,095,747 Memory system and method
9 8,040,164 Circuits and methods for programming integrated circuit input and output impedances
10 7,728,619 Circuit Method for cascading programmable impedance matching in a multi-chip system
11 7,719,908 Memory having read disturb test mode
12 7,684,257 Area efficient and fast static random access memory circuit and method
13 7,403,446 Single late-write for standard synchronous SRAMs
14 7,269,772 Method and apparatus for built-in self-test (BIST) of integrated circuit device
15 7,196,925 Memory array with current limiting device for preventing particle induced latch-up
16 7,146,454 Hiding refresh in 1T-SRAM architecture
17 7,142,477 Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses
18 5,656,861 Self-aligning contact and interconnect structure
19 5,620,919 Methods for fabricating integrated circuits including openings to transistor regions
20 5,483,104 Self-aligning contact and interconnect structure
21 5,172,211 High resistance Polysilicon load resistor
22 5,168,076 Method of fabricating a high resistance polysilicon load resistor
23 5,166,771 Self-aligning contact and interconnect structure
24 5,124,774 Compact SRAM cell layout
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