Electrical Engineer Air Force

ROBERT GREENE

**** * ***** #**

Santa Barbara, Ca 93105

Home Phone 805-***-****

Cell Phone 520-***-****

Email: **********@*****.***

SUMMARY

An integrated circuit designer with experience in analog and digital designs with many successful integrated circuits for cellular, ethernet, DSPs, and ADCs.

CAD TOOLS

Circuit Layout: Cadence, Mentor, ICED

Circuit Simulators: Smartspice, HSpice, Spectre

Highlevel Description Language: Verilog

Auto Place and Route: Chipgraph

FPGA Synthesis: Xilinx ISE and Altera HDL

System design: Matlab

CAD: AutoCAD

WORK HISTORY

Santa Barbara Focalplane, Contractor, Santa Barbara, Ca 2015

Designed, Spiced, and wrote Verilog model for an infrared focalplane array unit cell.

Calient Technology., Electrical Engineer, Santa Barbara, Ca 2013-2014

Wrote and synthesized a Xilinx FPGA to control the twisting voltage to a MEMS device.

Ridgetop Group, Inc., Electrical Engineer, Tucson, AZ 2007-2012

Designed a digitally calibrated fourteen bits, 400 kilosample per second successive approximation analog to digital converter.

Designed and tested a 250 ksample per second, twelve bits dual slope ADC.

Designed and laid out a canary chip that checks for radiation-caused threshold shifts, and a chip that detects radiation-caused field oxide leakage.

Researched and wrote the technical section of an SBIR proposal for a low-density parity check encoder.

Designing a sample and hold for a 20msps 12 bit pipeline ADC.

ITT, Engineer II, Vandenberg Air Force Base, CA 2005-2007

Debugged and tested range safety system.

Drew up and modified schematics in autocad in orcad for engineering change orders.

Wrote up a test plan for air force personal to check the system.

Raytheon Vision Systems, Principal Electrical Engineer, Goleta, CA 2004-2005

Designed a fourteen bits integrating triple-slope double ramp 250 kilohertz, analog to digital converter for an infrared sensor read out integrated circuit. Put my low area low power ADC on a space based focal plane array to bring out the unit cell voltages in digital. Designed and laid out a Hamming encoder for error detection and error correction. Made a low voltage differential swing circuit to extract high speed digital data off the chip.

Modified and reverified a microbolometer on schedule.

Platolabs Inc, Member of the Technical Staff, Campbell, CA 1996-2002

Designed and verified a CDMA back-end processor that went into first pass production.

Designed and laid out an audio codec sigma-delta modulator that was 1 square millimeter in a .35µ process and a 10/100/1000 ethernet chip.

National Semiconductor, Senior Engineer, Santa Clara, CA 1995-1996

Designed a frequency synthesis phase lock loop with 1ns of jitter.

Verified using Verilog a DECT baseband processor.

Motorola, Engineer, Schaumburg, IL 1984-1994

Designed the 24 by 24 multiplier for the DSP56000. Designed the filter for the sigma delta codec in the DSP56160. The requirement to work on the same chip as a quickly clocked DSP digital logic created a challenging noise immunity issue.

Worked on projects including a cryptography chip for secure radio, sigma-delta codec for a U-chip and a data converter for IS-54 digital cellular handset.

Designed DQPSK modulator and demodulator on the IS-54 handset chip as well as the interface to the host processor and the DSP. Low power was a requirement for long talk time.

PATENTS

Two patents assigned to Motorola on algorithms used inside the TDMA handset

chip design

PUBLICATIONS

Coauthor “A sixteen bit, one hundred and sixty kilohertz A/D converter using

sigma delta techniques” published in the Journal of Solid State Circuits, April 1990

issue

EDUCATION

BSEE, University of Illinois at Champaign-Urbana

MSEE, Santa Clara University 2002-2003

U.S. CITIZEN

SECURITY CLEARANCE

Contact this candidate