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IC Layout Designer

California, United States
January 28, 2018

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Northern California Area

408-***-**** cell: 408-***-****


To obtain a position as a Senior Layout Mask Designer


Over 20 years of experience in IC Layout Design

Detailed full chip planning, scheduling and chip leading

Analog, Digital, RF, ESD and Memory Layout experience

Standard Cell Library layout experience

Mentor IC Station and Cadence XL experience

Assura, Calibre experience

TSMC(6), IBM (2), JAZZ (2) and UMC(2) process experience

Excellent team player and highly motivated in all related layout assignments

Have Mentor and Cadence Layout Software Licenses


Dec - 2011 to Nov - 2012 // Feb -2014 to Dec - 2015//Aug - 2016 to Nov - 2017 R2 Semiconductor – Sunnyvale, Ca

Responsible for layout of Opamps, Vreg, Clamps, Switch Drivers and Charge

Pumps. The above circuits consisted of using extreme Analog techniques.

Used Cadence Virtuoso and Assura. TSMC Deep Nwell .18, 28nm and 40nm Process.

Dec – 2015 to June – 2016 – Cirque Corp – Salt Lake, Utah

Responsible for layout for ADC_Gref, ADC_Dac and ADC_Ref_Amp circuits.

Used Cadence VirtuosoXL and Assura verification. TSMC Deep Nwell .18


July - 2013 to Feb - 2014 - Echelon Corporation - San Jose, Ca

Responsible for layout of IO Pads and ESD structures. Modified many existing

analog layouts per engineering requests for better performance for the ADC block. Also responsible for adding in many level shifters and DCAPs to the

existing chip area. Used Cadence Virtuoso XL and Calibre verification.

SMIC .18 Process.

Nov – 2012 to July – 2013 – Qualcomm – Draper, Utah

Responsible for layout of bandgaps, delays, drivers, comparators, power supply’s and amplifiers with emphasis on matching, cross coupling, shielding and isolation. Used Cadence Virtuoso and Calibre verification. TSMC .18 Process.

Sept - 2010 to Nov - 2011 - Proteus Bio Medical – Redwood City, Ca

Responsible for planning and layout for a Medical Sensing ADC chip. This included layout for Bandgap, Power Supplies, OSC, Vreg, IO Pads and top

level chip hookup. Also Responsible for layout on 2V, 3V and 5V standard cell libraries. Used Cadence XL, Fujitsu .18 Process, Calibre and Assura verification tools.

Aug – 2009 to Apr – 2010 – Adept IC Solutions – San Jose, Ca

Responsible for planning and layout for a 12 bit ADC chip. This included layout

for SAR, COMP, DAC, IO Pads consisting of Analog, Digital logic and

2V, 5V standard cell libraries. Used Cadence XL, Assura and TSMC .18 Process.

Jan - 2009 to Aug - 2009 - SliceX - Draper, Utah

Responsible for layout on a ADC circuit. This included layout for Power Supplies, Bangaps, Bias, Amplifiers, PLL’s using extreme Analog matching,

common centroid, biasing techniques. Used Mentor IC Station, Calibre and

TSMC 90nm Process.

Jan – 2008 to Nov – 2008 - InVisage Technologies - Menlo Park, Ca

Responsible for layout on a Pixel ADC circuit. This included Digital Layout for

row and column cells for the Pixel Array using 1.2u pitch, 7 stages of timing

and comparator cells. Analog Layout for 7 stages of OPAMPS and MDAC’s.

Used Cadence Virtuoso, Assura and TSMC .11 process.

2000 to 2008 - Maxim Integrated Products (SP and C Group)

From 2000 to 2008, I worked with the Signal Processing and Conversion Group for approximately 6 months of each year.

I was responsible for planning, scheduling, leading, top level hookup and working with other lead designers on many Analog circuits.

This included Standard Cell libraries, Digital, Analog CMOS, BiCMOS and

I/O ESD pad cells.

I was in charge of the MAX5661 Single 16 Bit Dac. This included full chip

planning, scheduling, layout of many blocks and working with other layout

designer’s cells to incorporate in the circuit.

Maxim has extreme Analog techniques like matching, cross coupling, biasing,

guard rings that had to be used for layout.

Used LTL (onsite), Mentor (offsite) for layout tools and Dracula verification,

TSMC and various Maxim process rules.


Mr. Dave Maes 408-***-**** (Adept IC Solutions and Maxim – SP and C Group)

Mr. Larry Burns (R2 Semiconductor) 650-***-****

Mr Mauro Sirini 408-***-**** (Maxim- ISP Group)

Mr. Milton Dong 510-***-**** (InVisage and Foveon)

Mr. Danny Barlow 480-***-**** (Qualcomm)

Mr. Greg Martz 408-***-**** (Senior Layout Designer)

Mr. Jeff Berkman 408-***-**** (Proteus Bio Medical and Echelon Corporation)

Mr. Brent Quist 801-***-**** (Cirque Corp)


(consulted with the following companies from 1996 to 2016)

Adept IC Solutions Microsoft

Atmel Corp National Semiconductor

Advanced Micro Devices Nitron Corp

AMCC Phillips Semiconductor

American Micro Systems Pico Designs

Bitwave Semiconductor Proteus Bio Medical

Chips and Technologies Qualcomm

Echelon Corporation R2 Semiconductor

Fairchild Semiconductor SiTime Semiconductor

Four-Phase Systems Signetics

Foveon Inc. Sigma

Harris Semiconductor Siliconix

Hewlett Packard Slicex

Intel Corp. Synertek

Intersil Toshiba

InVisage Technologies Wafer Scale Integration

Lockheed Missile and Space Western Digital

Maxim Integrated Products Zilog Corp

Microchip Zoran Corp

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