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Design Engineer Project

Chennai, Tamil Nadu, India
January 17, 2018

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**, ***** ******, ********, ******* - *00 099

:***-********, : 09840181019, : STRENGTH:

Communication skills, hardworking, Responsible time management Leadership CAREER OBJECTIVE:

To be a part of a progressive firm offering opportunity for career advancement and Professional growth and which will help me gain sufficient knowledge. PROFESSIONAL EDUCATIONS:

2008 – 10 ME VLSI Design, College of Engineering Guindy, Anna university Chennai, 6.56 CGPA. 2004 – 08 B.Tech Electronics & Communication Engineering, Bharath University Chennai, 8.15 CGPA. 2002 – 04 HSC Maths & biology, W.P.A. Soudrapandian Hr. Sec School, Tamil Nadu state board, 66% 2000 – 02 SSLC, W.P.A. Soudrapandian Hr. Sec School, Tamil Nadu state board, 73% 2009 – 10 Diploma Software engineering, NIIT Perambur, Week end class, 75% EXPERIENCE:

Jul 2010 – Jun 2013 Assistant professor (ECE), Sri Muthukumaran institute of technology, Chennai. Sep 2013 – Dec 2015 System admin, Xpertii On Air GPS tracking solution, Chennai. Jan 2016 – Jan 2017 Design Engineer, Innovate Engineering Solutions, Chennai. Mar 2017 – to present Design Engineer, Techtilt info solutions Pvt, Ltd. Chennai. LANGUAGES KNOWN:

To Speak English, Tamil, and Telugu

To Read English &Tamil

Too Write English & Tamil


Operating system Windows 10, Windows vista, Red hat, Suse, Ubuntu Programming Languages C++, VHDL, Verilog, Basic in System Verilog & UVM Frequently used software


Xilinx 14.5, Cadence, Aletra Quartus, Tanner v15, Mentor graphics, Mat lab, Micro Wind

Technical Skills Digital design, FPGA, Static time analysis & ASIC HARDWARE SKILLS:

FPGA Sparton 3A / 3AN, Spaton 3E, Vertex 2 Pro, Vertex 4 Pro CPLD Cyclone II

Communication protocols SPI, I2C, RS232

Microcontroller Basic knowledge about PIC, ARM, ARDUINO PROJECT DETAILS:

Title Design and Synthesis of Combinational Circuits Using Reversible logic in Xilinx and CMOS technology

Skill Used Verilog language as well as VBB & GDI Techniques Project Details: i. The aim of this paper is to realize different types of combinational circuits using reversible circuit with minimum quantum cost. ii. Fredkin gates, Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, TR Gate and many more.

iii. Its applications in various fields which include Quantum Computing, Optical Computing, Nano technology, Computer Graphics, low power VLSI Etc.

Title Low power VLSI architecture for combined FM0/Manchester Encoder for reusability and FM0/Manchester Codecs

Skill Used Modified GDI Techniques

Project Details: i. It is also known as the Bi-Phase space coding technique. ii. It is not that simple as Manchester because of complex architecture. iii. Both these techniques are used to boost the signal and to maintain the dc balance.

iv. To combine both the techniques we are using the SOLS (Similarity logic oriented simplification) technique rather than combining with the MUX technique.

Title Hardware design of low power high throughput sorting unit Skill Used Verilog language, Xilinx 14.5 & sparton 3A/3AN FPGA Project Details: i. Since partial sorting with lower costs would be much more feasible than the complete sorting method for some applications. ii. High-speed computation usually raises power consumption drastically. To overcome that problem, a low-power, high-throughput, and modular hardware design of partial sorting network is presented. iii. Power dissipation is reduced by minimizing switching activities and signal transitions.

Title Programmable MISR modules for Logic BIST based VLSI testing

Skill Used Verilog language, Xilinx 14.5 & sparton 3A/3AN FPGA Project Details: i. The design of Programmable MISR(Multiple Input Signature Register) modules for Logic BIST based Very Large Scale Integration(VLSI) Integrated Circuit(IC) testing.

ii. The advancement in VLSI technology have made chip testing more complicated which has lead to the popularity of Logic Built In Self Test(LBIST) compared to Automatic Test Equipment(ATE). iii. The test patterns are not applied by ATE but are generated by inbuilt testing circuits. MISR is commonly used as an output response analyzer since it is alternative to n-parallel LFSRs.

Title Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic

Skill Used Verilog language, Xilinx 14.5 & sparton 3A/3AN FPGA Project Details: i. A basic cell is constructed by a logic block composed of a 2-data-input multiplexer and a switch box for data transfer between adjacent logic blocks by 8-near neighborhood mesh network.

ii. A multiplexer merged with a latch function is effectively employed for efficient fine-grain pipelined operation.

Title Content addressable memory early predict and Terminate pre-charge of match line

Skill Used VBB & GDI Techniques

Project Details: i. A novel content addressable memory (CAM) architecture with a simple but very effective pre-charge controller is presented. ii. This promises CAM with reduced power as well as improved search speed.

iii. CAM is a hardware search mechanism that pre-charges all its match lines (MLs) during the pre-charge phase, and a search is performed during the evaluate phase.

Title Auxiliary memory blocks for early dependability analysis of small processor based systems

Skill Used Verilog language, Xilinx 14.5 & sparton 3A/3AN FPGA Project Details: i. For this purpose, it is important not only to classify the faults, but also to understand the different faulty behaviours.

ii. Fault injection experiments are a powerful aid to identify and fix problems in the design of fault tolerance mechanisms, particularly when performed at early development phases.

Title Recent developments and design challenges of high-performance ring oscillator using GDI techniques

Skill Used VBB & GDI Techniques

Project Details: i. We emphasized the RO-based TDC and its variants including Vernier RO.

ii. We are compared both VBB technique & GDI technique. iii. used as building blocks in biomedical imaging, digital communication, and measurement instrumentation systems.

Title An efficient o(n) comparison-free sorting algorithm Skill Used Verilog language, Xilinx 14.5 & sparton 3A/3AN FPGA Project Details: i. We proposed a novel mathematical comparison-free sorting algorithm and associated hardware implementation. O(N) with respect to the sorting speed, transistor count, and power consumption. ii. Reduced no of components & Low power consumption. PERSONAL PROFILE:

Father’s Name Ramakrishnan R

Mother’s Name Rajam R

Date of birth 24th May 1986

Age 30 Years

Marital Status Single

Aadhar No 351409272313

Interested Listening to music, reading books, Gardening. Place :

Date :

Yours truely,

Kannan R

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