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Engineer Manager

Location:
Seattle, Washington, United States
Salary:
$110,000 +
Posted:
January 16, 2018

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Resume:

PAVITHRA KANNAN

*** Lenora Street, Apt #***, Seattle WA 98121 ● +1-206-***-**** ● p ac316h@r.postjobfree.com Experienced Senior Hardware Engineer with 6+ years of experience in logic verification and validation, seeking opportunities in hardware engineering areas such as architecture/design verification. EDUCATION

Master of Technology (M Tech) in M icroelectronics GPA: 9 .43/10.0 The Birla Institute of Technology and Science (BITS), P ilani, India (2013-2015) Graduation: May 2015 Bachelor of Engineering (B .E. ) in E lectronics and Communications Engineering GPA: 9.70/10

(Best Outgoing Student Award for the 2007-11 batch) M.S.Ramaiah Institute of Technology (MSRIT), B angalore, India (2007-11) Graduation: June 2011 Vidya Mandir Independent Pre- University College, B angalore, India (Class XII – 2007) 93.67% Aggregate Kendriya Vidyalaya Malleswaram (CBSE), B angalore, India (Class X: 2005) 90.60% Aggregate RELEVANT COURSEWORK

VLSI Design, Testability of VLSI, Computer Architecture, Embedded Systems, Hardware Software Co- Design. TECHNICAL SKILLSET

Functional Verification, Performance Verification, Hardware Validation Hardware Description Languages: Verilog, System Verilog, VHDL, Assembly Languages: C/C++, Perl, Unix/Linux shell scripting Tools: IBM proprietary verification tools and model simulators, Xilinx, MATLAB WORK EXPERIENCE

June 2016- Present I BM India Pvt Ltd, ISDL (India Systems Development Lab Bangalore, India Senior Hardware Engineer - Functional Verification Engineer Functional verification of the Open- CAPI data link logic

● Devised the verification environment from scratch. Coded the entire configuration setup for the DL logic, enabled new DL instance and ensure the links are up and training.

● Developed new test cases which resulted in the steep increase of events coverage (from ~30% to ~90%) - chip release critical activity. Testing of ~15 features such as lane reversal, lane swap, CRC generation, error injection, etc. Functional Verification Lead for CAPP (Coherently attached processor proxy) logic verification (Team of 5)

● Functional verification lead for the CAPP logic in IBM's P9 processor. Developed the test plan for the project with timelines, resource allocation and impact

● Usage of IBM’s agile methodology to track the Project progress

● Responsible for testing the upgraded TLBI snoop logic. Developed verification testbench - generators, monitors and drivers. Many critical bugs (~30) were identified in the pre- silicon phase resulting in a seamless bring up and validation in the post- silicon lab testing.

● Verification of the translation unit (XSL) – enabled the translation in the end-to-end CAPI environment. Essential component in enabling the CAPI logic at the chip level verification.

● Complete ownership of the verification of the error recovery feature at the overall Chip level, r esulted in a bug free environment in the post-silicon chip:

- Bring up the new CAPI verification environment from scratch. Identifying new test cases and develop driver code and verify the logic across multiple units, and set up regressions.

- This test bench involved 3 major logic blocks and required collaboration with the related teams and stakeholders across USA, Germany and Haifa.

- This feature was verified for the first time at a chip level, in IBM’s Power verification history. It was assigned as a critical, chip-release gating project and was accomplished in a month’s time.

- Logic verification of Error injection and detection (ECC/CRC), verify the error report registers and fault- in registers of each sub- unit in the logic and fail recovery features in CAPP logic. Identified ~20 logic bugs in the pre- silicon testing.

Mar 2014 – June 2016 IBM India Pvt Ltd, ISDL (India Systems Development Lab), Bangalore, India Hardware Engineer -Functional Verification Engineer

● Functional Verification of the CAPP unit on IBM’s P9 processor. Verification environment bring up and develop clock settings new processor generation from scratch.

● Developed interface monitors to directly connect the logic to IBM’s fabric bus, as opposed to the previous generation processor where CAPP was a sub-unit in the crypto logic. Involved several fabric addressing and tag changes.

● Devised the CAPP micro-op table generator and PSL’s (power service layer) address generator codes to incorporate the updates in the new fabric logic.

● Provided memory initialization support for unit and chip level verification.

● Logic Verification of the CAPP unit on IBM’s Naples processor –Developed the hardware test bench to enable the dual Capp mode and ensure scalability. Enabled the seamless integration of the verification test bench at the Chip level verification. This mode was introduced in Naples and is used in all the shipped systems.

July 2011 – Mar 2014 IBM India Pvt Ltd, THD (Technology & Hardware Development), Bangalore, India Hardware Performance Verification Engineer

● Performance Verification of the Accelerator Switch Board Unit and determine its effectiveness in SMP modes.

● Performance Verification of the Memory controller and Memory Buffer Chip units of IBM's Power series processor(P8), to ensure the bandwidth and latency performance metrics are as per the architected values - Determined the effectiveness of the LRU algorithm

● Developed a Power-performance analysis in pre-silicon which proved highly critical to the Power and Memory Lab teams, and aided them in identifying the the optimal Power Mode settings in the post- silicon lab testing.

● Owned the first time performance verification of the Cache Cleaner and Refresh Avoidance features introduced in the IBM’s next generation processors (P8) - Created shell scrips to generate test-case patterns.

● Added PCIe command initiator functionality to support the PCIe related commands for fabric performance verification.

● Performance Analysis; Core and Chip level – Analyze and triage the performance metrics obtained from the hpc memory and spec workloads run on VHDL behavioral models vs performance models

● Performance analysis of Java workloads on IBM’s Z processors – Determine and analyze SMP performance metrics on Z-Helix and Z-Sphinx machines.

● IBM Internship SPOC: Member of the IBM-THD's University Relationship Team, and in-charge of the PhD fellowships and Faculty Awards programs in IBM

PAPERs/POSTERs

● Technical Paper “E xperimental characterization and power- performance optimization of a POWER based server class memory subsystem” p resented and published at the IEEE INDICON 2017.

● Finalist of the Poster Presentation Event at the G race Hopper Women's conference India, in Dec 2012 - Methodology to decrease pre to post silicon “design for test” efforts, on the usage of I/O tool kit tools and its usefulness in the pre- to- post silicon phase mapping of performance tests/workloads.

● Selected amongst the top 100 cognitive project proposals in the IBM Watson Cognitive Build challenge OTHER PROJECTS

● Undergraduate Research – Real Time Hand Gesture Recognition (Sep 2010- June 2011) Developed a computer vision algorithm which recognizes dynamic hand gestures using data captured from the webcam, in real-time. T he algorithm implemented in real- time on an ARM based Beagle board (by Texas Instruments), as a working prototype for hand gesture recognition on embedded systems.

o Short-listed among top 20 projects over the country in the national-level “Jed-I Project Challenge”, at Indian Institute of Science, Bangalore, India, for the year 2011

o Awarded Best Paper for paper presentation at national-level conference “KnowledgeUtsav”, held in Bangalore, India, in August 2010.

o Awarded second best project of the year by ECE Dept, MSRIT.

● Implementation of a Hand Gesture Recognition Algorithm (July- Aug 2010) Static hand gesture recognition using the concept of orientation histograms and the detection of direction of motion by computing the center of gravity of the image sequence from a live stream of camera input.

● GPS Navigation System (July- Aug 2009)

Interfaced 8051 micro controller to a GPS receiver, parsed the data in the NMEA form to extract the longitude and latitude from the GPS string (C Program). This information was used for navigating vehicles ACHIEVEMENTS & HONORS

● Execution Excellence Award- 2017, for delivering amazing results on CAPI and Open CAPI

● Star of the Month Award – 2016, at IBM for t he quick ramp up and getting the XSL online in CAPI environment, in a very short time for Nimbus DD1.

● Manager’s Choice Award – 2015, at IBM for the practice D are to Create Original Ideas

● Manager’s Choice Award – 2015, at IBM for the practice S how Personal Interest

● Ranked 1st in Class XII Board Examinations, at the school level. OTHER ACTIVITIES

Accomplished Bharatanatyam Dancer, Carnatic (Indian classical) singer and theater artist. Trained in the art form for the last 15 years. Have performed extensively at several festivals across India.



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