Engineer Electrical
Resume:
Sidhant Poddar
************@*****.***, 716-***-****, linkedin.com/in/sidhantpoddar
**** ******* ***, #*, *********, CA 94086
OBJECTIVE:
Seeking full-time employment opportunity as an Electrical Engineer focusing towards Hardware Test and Development which utilizes my extensive knowledge and training.
EDUCATION:
Master of Science, Electrical and Electronics Engineering February 2017
University at Buffalo, State University of New York GPA: 3.8/4.0
Bachelors of Engineering, Electrical and Electronics Engineering July 2015
PES Institute of Technology, Bangalore, India GPA: 8.93/10
TECHNICAL PROFICIENCIES:
Programming Languages : C/C++, Python, MATLAB, Verilog, Embedded C.
Operating Systems : Windows XP/7/8, Linux, Android.
Software Tools : Microsoft Office, Xilinx ISE, LT Spice, Agilent ADS, Modelsim - Altera Quartus, Eclipse, Code Composer Studio.
Technical Knowledge : TCP/IP protocol stack, UDP, Ethernet, Analog Circuits, Digital Systems and logic gates, Digital Signal
Processing, Spartan 3E and DE2i-150 FPGA board, Function Generator, Communication Electronics, Oscilloscope, Routers and Switches
Computer Architecture, Logic Design, Programming MSP 430 Microcontroller using C, ADC, DAC, PLLs, DHCP, ARP, Signal
generators, Multi meters, Logic Analyzers, Bread Boards, Oscilloscope, Spectrum Analyzers, RTL Design using Verilog, Design using QSYS,
Antenna Design using Agilent ADS, Schematic diagram and Circuit Design LTSPICE, Programming FPGA boards using Xilinx ISE and Quartus.
WORK EXPERIENCE:
Firmware Test Engineer Intern at Cepheid Inc., Sunnyvale, CA, United States. June 2017 – August 2017
Responsibilities:
I was responsible for testing the Firmware being developed for Cepheid’s Next Generation Molecular Diagnostic Devices. I performed Tests to check the functionality of NFC (Near Filed Communication), Battery of the device, Temperature Sensors and USB Communications between different parts.
Intern at Rolta Ind Pvt. Ltd., Mumbai, India. June 2014 – August 2014.
Responsibilities:
IT Transformation Services: I was responsible for Computer Assembly and software maintenance, I also got a chance to learn about the operations of a data center and how data centers are maintained
Defense Services: I also had the Opportunity to work for the defense Sector of the company providing defense solutions for the Indian Armed Forces.
Trainee at Independent Business Machines Pvt. Ltd., Chandigarh, India. May 2013 – August 2013.
Responsibilities:
I was responsible for Computer Assembly and software maintenance for both Desktops and Laptops.
ACADEMIC PROJECTS:
Network Attached SD Card Storage Device:
Read/ Write and List the contents of an SD Card using Altera Quartus which is on the DE2i-150 FPGA board using a PC connected to it through a Crossover Ethernet cable.
OFDM Implementation using a DE2i-150 FPGA board:
Orthogonal Frequency-Division Multiplexing technique implemented using Altera Quartus on a DE2i – 150 FPGA board.
Electronic Lock:
An Electronic Lock implemented using Xilinx ISE on Spartan 3E FPGA board.
Implementation of Various Routing Protocols on NS-3
Wireless routing protocols such as ALOHA, CSMA/CA have been implemented on NS-3 using C++. And Wireshark has been used to realize the flow of data in the network for various applications of internet such as the web, email etc.
Dual Band Patch Antenna Array
Created Dual Band Patch Antenna Array for 2.4GHz and 5GHz frequencies using Agilent ADS for the simulation of design and to analyze frequency momentum of the antenna.
Design and Implementation of Gilbert Cell Mixer Circuit, AM modulator, Class C tuned Amplifier
Circuits were designed using LT Spice and were practically implemented using Bread Boards, Regulated DC supply, Signal/function Generator, Oscilloscope.
Simulation of PAPR reduction techniques in OFDM using Matlab
OFDM systems are known to have a high peak-to-average ratio (PAPR) when compared to single carrier systems. Different PAPR reducing techniques were studied and simulated using Matlab.
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