Design Engineer Layout

BERNARD F. BENTLEY, JR.

**** ******** **** *****

Antioch, CA 94531-8336

925-***-**** 925-***-**** 209-***-****

***********@*****.***

OBJECTIVE: SR. I.C. LAYOUT DESIGN ENGINEER

PERSONAL STATEMENT

I am an enthusiastic, dedicated worker able to follow instructions well. I have the ability to lead, instruct, and assist in obtaining project goals. I am detail oriented as well as possessing the ability to accomplish tasks in an accurate and timely manner.

PROVEN ABILITIES

• Lead, schedule and plan circuit projects that are both efficient and cost effective within time scheduled.

• Supervise and instruct team members through all phases of project.

• Create layout that can and will save silicon waste and dollars.

• Create the tightest compaction of layout possible.

ACHIEVEMENTS

• Performed layout of Analog and Digital circuits in 250nm, 180nm, 130nm, 90nm, 65nm, 45nm, 40nm, 28nm and 10nm/finfet technologies

• Performed layout of RF/Analog circuits.

• Performed layout of Memory circuits. I.e., ROMS, EPROMS, EEPROMS, RAMS, DRAMS and SDRAMS.

• Performed layout of Data Path circuits.

• Performed layout of Analog circuits. i.e., Level shifters, Opamps, Voltage References, Voltage Generator, Oscillators, Comparators, Bias Generators, ADC, DAC, etc.

• Performed layout of Digital circuits. i.e., Flip-Flops, Latches, basic and complex logic.

• Performed layout of BiCmos and Mixed Signal circuits.

• Performed layout of IO’s and ESD structures analog and digital.

• Created IO libraries for analog and digital circuits.

• Layout using: 250nm, 180nm, 130nm, 90nm, 65 nm, 45nm, 40nm, 28nm and 10nm/finfet processes up to (13+) layers of metal.

• Created Standard Cell libraries in 250nm, 180nm and 130nm processes.

• Led and Supervised Jr., intermediate and Sr. layout designers on multiple projects.

• Performed layout at chip level from inception to finish on multiple projects.

TOOLS

DESIGN TOOLS:

• Cadence: Opus, Virtuoso and Virtuoso XL (DLE), Virtuoso XL and GXL versions 6.1.13, 6.1.14, 6.1.15 and 6.1.16.

• Mentor Graphics: ICStation (layout tool)

• Expert (PC based layout tool)

VERIFICATION TOOLS:

Synopsys: PVS

• Mentor Graphics: Calibre (DRC, LVS and ERC) latest versions used.

• Mentor Graphics: ICVerify (DRC and LVS)

• Cadence: ASSURA, DIVA and Dracula (DRC and LVS)

• Avant! Hercules (DRC and LVS)

OPERATING SYSTEMS:

• Linux

• UNIX

• Windows NT

EMPLOYMENT

1.Intel, Inc., 101 Innovation Dr., San Jose, CA 95134

(Direct) 06/20/2016 – 06/09/2017

Digital Core layout in 10nm finfet process.

2.GigOptix, Inc., 12824 Earhart Ave., Auburn, CA 95602

(Contract) 04/25/2016 – 06/19/2016

Layout of Analog blocks for circuit project using 45nm process.

3.PA Express, LLC, 2328 Walsh Ave., Santa Clara, CA 95051

(Contract) 12/2/2015 – 04/07/2016

Layout of Power Amplifier circuits (28nm).

4.Entropic Communications, 6290 Sequence Dr., San Diego, CA 92121

(Contract) 09/16/2013 – 10/17/2013

Tape out Layout Support.

Layout of IO blocks for Entropic’s circuit project tape out (28nm).

5.IO Semiconductor, Inc., 4350 Executive Drive, Suite 200, San Diego, CA 92121

(Contract) 02/26/2013 - 04/07/2013

Tape out layout support for Test chip.

Layout Design Rules revision layout.

6. Inphi, Corp., 112 S. Lakeview Canyon Road, Suite 100, Westlake Village, CA 91362

(Contract) 01/17/2012 – 5/30/2012

Performed layout and verification of analog 1.2 volt standard cell library.

Performed layout and verification of DDR4 project for the RCD group

7.Qualcomm Inc., 5775 Morehouse Drive, San Diego, CA

(Contract) 06/22/2011 – 12/29/2011

Performed layout for the Digital Design Group using (28nm) HPM technology.

Performed layout and verification of DDR Phy project.

8.ViMicro Corp., 6540 Lusk Blvd., Suite C168, San Diego, CA 92121

(Contract) 04/19/2011 – 04/29/2011

Performed layout changes to their misc_dig_interface block adding level shifters, pins and misc.

Performed layout changes to four inductors.

Performed DRC and LVS of the above layout changes.

7. Qualcomm Inc., 5775 Morehouse Drive, San Diego, CA 92121

(Contract) 7/26/2010 – 11/17/2010

Performed layout and verification of RF analog/Analog circuits in 28nm wireless technologies.

Performed layout of TX, RX circuit blocks as well as, Level Shifters, Comparators and DAC’s.

8. Solarflare Communications., 9501 Jeronimo Road, Suite 250, Irvine, CA 92618, 949-***-**** Ext. 2010

(Direct) 07/28/08 to 06/03/10

Performed layout and verification of Analog and Digital circuits in 65nm, 45nm and 40nm technologies.

Performed layout of TX, RX circuit blocks as well as, SerDes, PLL’s, Level Shifters, Comparators, ADC and DAC’s.

9. Quellan, Inc., 2880 Lakeside Dr., Suite 250, Santa Clara, CA 95054, 408-***-****

(Direct) 01/08 to 7/21/08

Performed layout and verification of RF/Analog circuits TSMC 180nm and 130nm - 1.3v and 3v circuits.

Performed layout of TX, RX circuit blocks as well as, PLL’s, Level Shifters, Comparators, ADC, DAC’s and IO’s and ESD structures.

10. Qualcomm, Inc., 675 Campbell Technology Dr., Campbell, CA 95008

(Contract) 03/07 to 12/07

Performed 65nm RF/Analog layout at lower level cell to upper block and top level using bump pad technology.

Performed layout of TX, RX circuit blocks as well as, PLL’s, Level Shifters, Comparators, DAC‘s, IO and ESD structures.

11. Tahoe Semiconductor, Inc., 12840 Earhart Ave., Suite 140, Auburn, CA 95602, 530-***-****

(Contract) 01/07 – 01/07

Performed layout and verification of variable gain analog block for tape out.

12. T-RAM Semiconductor, 620 North McCarthy Blvd., Milpitas, CA 95035, 408-***-****

(Contract) 07/05/06 – 07/31/06

Performed layout and verification of Digital Memory blocks.

Performed layout and verification of Digital Memory Pad cells.

13. Amalfi Semiconductor, 475 Alberto Way, Suite #200, Los Gatos, CA 95032, 408-***-****

(Contract) 11/22/04 – 01/10/05

(Direct) 01/10/05 – 05/04/06

Performed layout and verification of RF/Analog circuits TSMC 180nm - 1.3v and 3v circuits.

Performed layout of TX, RX circuit blocks as well as, PLL’s, Level Shifters, Comparators, DAC, IO’s and ESD structures.

14. W J Communications, 401 River Oaks Parkway, San Jose, CA 95134, 408-***-****

(Contract) 04/26/04 – 07/09/04

Performed layout of Analog blocks, OpAmp, Bandgap, lock_detect, CML, 5 bit and 8 bit DAC.

Performed verification of above blocks.

15. Motorola, 6501 W. William Cannon Drive, Austin, TX 78721, 512-***-****

(Contract) 04/28/03 – 05/23/03

Performed layout of Analog Voltage Reference block, using Matched, Common Centroid, and

Interdigitation techniques.

Performed layout of test devices adding probe pads for testing.

Layout out was also done incorporating several metal options.

Layout using 130nm process with six layers of metal.

16. Net Logic Microsystems, 450 National Avenue, Mountain View, CA 94043, 650-***-****

(Contract) 07/15/02 – 10/09/02

Performed layout of CFP Memory circuit.

Performed layout of Digital circuits. i.e., Flip-Flops, Latches, basic and complex logic.

Performed layout using 130nm processes up to eight layers of metal.

17. Synaptics, 2381 Bering Dr., San Jose, CA 95131, 408-***-****

(Contract) 04/01/02 – 04/15/02

Performed layout of Analog circuits. 2 Opamps and 1 Voltage Reference blocks.

18. National Semiconductor Corp., 2900 Semiconductor Dr., Santa Clara, CA 95051, 408-***-****

(Direct) 07/00 – 12/01

Performed layout of Analog circuits. i.e., Level shifters, Opamps, Voltage References, ADC and DAC etc.

Performed layout of Digital circuits. i.e., Flip-Flops, Latches, basic and complex logic.

Performed layout of IO’s and ESD structures analog and digital.

Created IO libraries for analog and digital circuits.

Performed layout using180nm and 130nm processes up to six layers of metal.

Created Standard Cell libraries in 250nm, 180nm and 130nm processes.

Performed layout of Data Path circuits.

19. National Semiconductor Corp.

(Contract) 02/00 – 07/00

Performed layout of Digital Circuits. 50 Flip-Flops

EDUCATION

• Cadence advance training on versions 6.1.13 and 6.1.14. 03/09 - 07/09 and 01/10 - 04/10

• AVANT! Training (Apollo Fundamentals Training), Fremont, CA - 09/09/01 – 09/11/01

• Silicon Valley Small Business Institute, San Jose, CA - 02/94 – 11/94

• Motorola University, Austin, TX – 08/90 – 12/93

• University of ISS, Research Triangle Park, NC – 04/93

• West Valley College, Cupertino, CA – 09/87 – 05/88

• Institute For Business And Technology, San Jose, CA – 09/79

• Kansas City, Kansas Community College, Kansas City, KS – 09/78

• Galileo Adult School, San Francisco, CA – 02/74

MILITARY

• UNITED STATES AIR FORCE *** HONORABLE DISCHARGE *** - 12/76

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