Project Team Leader

Curriculum-vitae

M.V.SRINIVASA REDDY E-mail: *********.****@*****.***

Mobile: 966-***-****.

Career Objective:

Intend to build a career with leading corporate of hi-tech environment with committed & dedicated people, which will help me to explore myself fully and realize my potential.

Academic Profile:

Year

Degree

School / University

Percentage

2015

M. Tech (VLSI)

Narayana Engineering College,

Nellore

79.00%

2012

B. Tech (ECE)

Sri Sai College of Engg &

Technology, JNTU Anantapur.

75.98%

2008

Board of Intermediate Education, Andhra Pradesh

Sri chaitanya IIT

Hyderabad.

75.00%

2006

Board Of SSC, Andhra Pradesh

Kesava Reddy Residential,

Panyam

87.00%

Work Experience:

1.Present : Working as an Instrumentation Engineer in Sagar Cement Ltd from 01-02-2017.

2.Previous : Worked as an Assistant Professor in Sir CV Raman Engineering College from 05-06-2016 to 30-11-2016.

Technical Skills:

Hardware Programs : VHDL, Verilog

Micro Controllers : 8051, 8052

Micro Processors : 8085, 8086

Technical Subjects : Digital Electronics, Instrumentation, VLSI, Embedded

Systems, Network Analysis, Communications

Personal Skills:

I have been able to adapt quickly and efficiently to my working environment

Really motivated and always ready to learn new things

I am flexible and adaptive to project dynamics & self-learner of assigned tasks.

I can Able to plan and execute tasks with minimal supervision

Team-player, will work well in a group environment and keeps management updated on status, challenges & risks.

Academic Project Details:

M. Tech Project:

Title : IMPLEMENTATION OF DIGITAL FILTER USING ADC AND DAC OF

SPARTAN 3E FPGA BOARD

Environment : VLSI, Signal Processing

Team Size : 1

Duration : 1 Year

Description :

The objective of this project is to interface the onboard ADC and DAC available in the Spartan 3E FPGA platform, so that the real signals can be processed by the FPGA board. This will facilitate to implement digital signal processing in real time and hence wide range of filtering; noise removal systems can be implemented with ease.

B. Tech Project:

Main Project:

Title : DESIGN SPACE EXPLORATION OF HARD DECISION VITERBI ALGORITHM

Environment : VLSI, Viterbi algorithm

Role : Team leader

Team Size : 5

Duration : 3 Months

Description :

Viterbi algorithm is widely used as a decoding technique for convolution codes as well as a bit detection method in storage devices. The design space for VLSI implementation of Viterbi decoders is huge, involving choices of throughput, latency, area, and power. This work analyzes the design complexity by applying most of the known VLSI implementation techniques for hard-decision Viterbi decoding to a different set of code.

Mini Project:

Title : ACCIDENT IDENTIFICATION USING GSM

Environment : Embedded System

Role : Team leader

Team Size : 5

Duration : 1 1/2 Months

Description :

The main intention of this project is to know the accident at any place using GSM Network. The GSM based vehicle accident identification module Pressure Sensor and a GSM modem connected to microcontroller. GSM technology is used to establish cellular connection.

Personal Details

Name : M.V. Srinivasa Reddy

Father’s name : M. Pulla Reddy

Date of Birth : 5th Aug 1991

Gender : Male

Nationality : INDIAN

Languages known : English, Telugu and Hindi

Hobbies : Gardening, Surfing Net, Playing Games, Listening music

Strengths : Quick Learner, Self Confident & Taking initiative steps

Permanent Address : B/O: M. Rameshwara Reddy, D.NO: 1/645-3,

Guru Lodge Street,

Near RTC bus stand, Tadipatri,

Anantapur,

Andhra Pradesh,

India

515411.

Declaration

I hereby declare that all the information furnished above is true to the best of my knowledge.

Place: Date: (M.V. Srinivasa Reddy)

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