Senior DFT Engineer

Resume

Ram Mohan Verma

Senior DFT Engineer.

Cientra Tech Solution Pvt Ltd. Mobile 973-***-****

Profile Summary

M.Tech (Microelectronics) with 5 years of experience in DFT domain.

Worked on Scan Insertion and coverage improvement for Qorvo.

Worked on TAP validation for GNRD project for Intel.

Direct Experience in Silicon Bring up and post-silicon validation on ATE.

Worked on pattern debug and validation (JTAG, BScan) of a Soc wafer and package and wafer level.

Have experience in Verilog, VBA scripting and C languages.

Work Experience

Senior DFT Engineer, Cientra Tech Solution Pvt Ltd.

Client worked: Qorvo

Duration: Nov 22 - June 2023

DFT Engineer

oATPG pattern generation, timing simulation and debug for the Pegasus Project.

oScan transition pattern count reduction and coverage improvement upto 95% is done for the top level.

oVCS tool is used for the simulation and verdi for the visualization of the signals waveforms, and connectivity.

Client worked: Intel

Duration: July2021 - AUG 2022

DFT Engineer

oTAP pattern generation, Simulation and debug for the GNRD Project.

oDebug is done for the different tap like, TAP_NAC_DFXN, DFXS, IRC, RMN0, RMN1, VRPCPK, VRPCPM, BISERTAP_CPK, CPM, HLP etc.

oSynopsys VCS tool is used for the simulation and verdi is used for the visualization of the signals waveforms, connectivity, and programmed registers value.

Client worked: Intel

Duration: July2019 - June 2020

DFT Engineer

oMBIST pattern Simulation from the top for TRC Project, and debug for the blocks like hp_ul_txrxcc, ss_hp_mac, dl _eta_dpd, gic_wrap etc.

oDebug is done for the block which includes power supply issues, clock checks, mbistpg_go and done and all controllers checks for the block etc.

oSynopsys VCS tool is used for the simulation and verdi is used for the visualization of the signals waveforms and connectivity.

oWorked on ATPG/SAGE pattern generation and validation.

Client worked: Intel

Duration: July 2018 - Dec 2018

DfD Engineer.

oImplemented the VISA at SoC level for the DashG Project.

oNorthpeak IP Integration at SoC for the DashG Project.

Synopsys -VCS is used for the visual analysis of the waveform and signal connectivity.

ATE Engineer, Tessolve Semiconductor Pvt. Ltd

Client worked: Qualcomm

Duration: Jan 2017- 03-Oct 2017

oWorked on Silicon Validation on JTAG, Boundary Scan, and the Functional block for the Qualcomm HwakEye (WiFi Router) Project on verigy platform. This work includes the TestFlow Creation, Timing file optimization, Debug of the patterns at multiple Supply Specs and the temperature, data collection and analysis.

oAnalysis of the data, taken across PVT corners to further improve the yield.

Client worked: AMD

Duration: Oct 2014- Dec 2016

oWorked on Scan pattern translation and validation.

oWorked on the validation of JTAG, BScan block for the AMD Kingston and Bristol Ridge Project on Verigy and Sapphire platforms. This includes Test Suit development, Production data analysis, and yield report preparation.

oPlatform conversion for the Stoney Ridge project from Verigy test Program to the Sapphire platform,

Area of Interest:

1.JTAG, Scan, Boundary Scan and Functional Blocks.

2.To work on Scan Insertion and ATPG.

3.Device Characterization.

Details of Technical Qualifications

M.Tech (Microelectronics / 2013) from Indian Institute of Information Technology, Allahabad with 8.05 CGPI.

B.Tech. (Electronics/ 2011) from Vishveshwarya Institute of Engineering and Technology, Ghaziabad, with 65.16%

Certificates and Achievements:

1.Gate 2010 & 2012 qualified.

2.Junior Research Fellow and NET Qualified in 2013 Conducted by UGC with over 99.52 Percentile.

3.Research paper published in Applied Physics Letters (APL), “Electrical Characterization of the Metal Ferroelectric Oxide Silicon Metal Ferroelectric Nitride Silicon Gate Stack for the Ferroelectric FET” based on the M.Tech project.

Professional Attributes:

The ability to remain calm and objective in all situations.

The ability to quickly identify and resolve problems.

Able to work autonomously and in a team environment.

Good team member, positive attitude and result-oriented Self-motivated, quick learner, willing to adapt to new challenges & new technologies.

I hereby declare that all the statements made in the above application are true to the best of my knowledge.

Place: Bangalore (Ram Mohan Verma)

Date :

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