Engineer Professional Experience

SRISIDHARTH KANNAN

619-***-**** • ********@*****.*** • https://www.linkedin.com/in/srisidharthkannan

OBJECTIVE

Candidate with professional experience in ASIC design/verification looking for a full-time position as an ASIC Design/ Verification Engineer.

ACADEMIC QUALIFICATIONS

Master of Science in Electrical Engineering (MSEE in VLSI) May 2016

San Diego State University, San Diego, CA (SDSU)

Coursework: VLSI Circuit Design, ASIC Design, VLSI System Design, Signal and Power Integrity, RF Circuit Design.

Bachelor of Engineering in Electronics and Communication Engineering March 2011

Anna University, Chennai, India

TECHNICAL SKILLS

Languages and Methodologies: Verilog, System Verilog, OVM, UVM, C, C++

EDA Tools: Cadence NCSim, Cadence Virtuoso, Mentor Graphics-IC station, Synopsys VCS, Xilinx ISE, Altera, Model Sim

FPGA Tools: Logic analyzer, Spectrum analyzer, Oscilloscopes, Signal tap, Jtag tools, Multimeters, Xilinx and Altera

Protocols: RAPIDIO, SPI, I2C, UBUS, USB3.0

PROFESSIONAL EXPERIENCE

FPGA Engineer at YuneecUSA, San Diego, California March 2016 – present

Hardware RTL Design in Verilog

Verifying and Integration of FPGA and CPLD sub blocks.

Board level debugging using oscilloscopes and software level debugging using signal taps.

Interact with software team to enhance test plans and test coverage for full system level testing.

Technical Intern Verification Engineer at Broadcom Corporation, Irvine, California June 2015 – August 2015

Conversion of Verilog testbench to UVM testbench.

Own the existing USB simulation environment, run regression and debug to support new chip development teams.

Design/Verification Engineer at Wipro Technologies, Bangalore, India June 2011 - June 2013 Projects:

Intellectual Property (IP) Verification in UVM (12 months)

oTop level functional verification and successful running of IO and Logical blocks.

oDesign and Integration of Testbench Components, Assertions, Sequences, Debugging and Regression analysis.

oDeveloped Scoreboards for the IO blocks.

oDeveloped constrained random Testcases in UVM and worked on coverage groups.

System on Chip (SOC) Verification in OVM (8 months)

oTop level functional verification of the memory block.

oDesigned and integrated constrained random Testcases and sequence in OVM.

oPerform debugging and resolve issues that arise from simulation regression.

Designed, executed and verified SRAM in Verilog. (4 months)

ACADEMIC PROJECTS

Design of FIR and IIR filters (Tools: Xilinx ISE, Cadence NCSim, MATLAB) Spring 2014

The design is parameterized using fixed point and floating point multiplier and adder circuits with second order systems.

The filters are pipelined and designed in both direct-forms 1 and 2 and implemented with time-multiplexed cascaded SOSs.

Design of ALU (Tools: Xilinx ISE) Spring 2014

The ALU can perform 16 different arithmetic and logical operations.

Designed using structural Verilog model by instantiating the logic unit, arithmetic unit, and multiplexer in a top-level module.

Design of an 8-bit Barrel Shifter (Tools: Xilinx ISE) Spring 2014

The barrel shifter is an 8-bit which receives two selection signals, one is to decide the direction in which it has to shift and the other is to switch the shifting operation between arithmetic and logical shift operations.

8*8 Booth Encoded Multiplier (Tools: Cadence Virtuoso) Fall 2013

The design of a Modified Booth Encoded multiplication allows for smaller, faster multiplication by reducing the number of partial products.

Booth Encoder, Partial Product Generator, Half Adder, Full Adder, Carry Look Ahead Adder (CLA) and Carry Select Adder are presented in this system.

Layout Design of D-Flip Flop and Priority Encoder (Tools: Mentor Graphics-IC station) Fall 2013

The designs are implemented using both p-well and n-well technology with latch-up protection in all the cells.

The circuits are made certain to pass the Design Rule Checks and scalable CMOS (ADK) design rules.

Design of Analog to Digital Converter (Tools: Mentor Graphics-IC station) Fall 2013

Designed 8-bit SAR ADC at 80MS/s in 60nm CMOS technology.

Analyzed design trade-offs like sampling rate, noise and jitter.

The clock signals are derived from a voltage controlled ring oscillator.

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