Hardware Design Engineer, RF Design, Board Design

Matthew Baumgartner

****.*****.***********@*****.*** 541-***-**** www.linkedin.com/in/matthew-baumgartner-97b68417/ PROFESSIONAL EXPERIENCE

Hardware Design Engineer, Probe Solutions June 2012 – Present Tektronix, Inc., Beaverton, OR

Hardware lead in creating a test fixture for engineering and manufacturing development on a new probe interface

(TekVPI+). System requirements were to control and generate 5V and 10-14V power supplies, with current/voltage monitoring, all controlled through software, with USB 2.0 enabled communication to the probe.

Assisted manufacturing in evaluating high-end performance probes and worked with engineering to test prototypes of a developing new product. Handled debugging the test station, which used a Vector Network Analyzer (up to 60 GHz), multiple Keithley power supplies and DMMs, and Fluke pulse generators.

Designed a lower cost probe from an existing 1 GHz passive probe. Modified key specs by switching out the probe’s cable to a cheaper and more stable model, resulting in a 40% reduction in product costs and an increase in product reliability.

MECOP Engineering Intern, Probe Solutions June 2011 – December 2011 Tektronix, Inc., Beaverton, OR

Researched and prototyped a more reliable and low cost cable, up to 200 MHz. Used SPICE simulation, skin effect calculations, and time-domain reflectometer (TDR) measurements to analyze the cable and prove the cable was capable of reaching higher bandwidths, with the correct termination.

Assisted Sampling Scopes group with FPGA design modification to speed up communication processes using Altera tools. The core of the change was to switch the existing board’s clock to a faster speed, using System Verilog. MECOP Engineering Intern, Wafer Station, PCBs March 2010 – September 2010 Cascade Microtech, Beaverton, OR

Designed and implemented testing software and fixtures for manufacturing to test PCBs before they reached assembly and were installed into the wafer station system. Achieved by using LabView to generate high level code blocks to test the throughput of the most error-prone boards, including a randomized function to exercise the board more thoroughly.

EDUCATION

Oregon State University, Corvallis, OR

Bachelor of Science in Electrical and Computer Engineering, June 2012 Multiple Engineering Cooperative Program, Integrated Circuits Track LEADERSHIP/SERVICE

Senator, Associated Students of Oregon State University September 2008 - June 2010

Introduced and voted on student legislation, consisting of rules for campus (No Smoking Policy) or representation of the student body on broader policies, such as support for different state or federal laws. Executive Board Member, Sigma Phi Epsilon Fraternity November 2008 - November 2009

Participated in operating and governing the Oregon Alpha chapter, specifically with the title of VP of Communications. Kept meeting notes, communicated timings of events, and managed the chapter’s internal internet, including our email list.

TECHNICAL SKILLS

PCB Design (Cadence Allegro tools) ● MATLAB ● Ansys HFSS ● Power Supply Design ● SPICE Simulation (LTSPICE, HSPICE, MICROCAP) ● Python ● Test Equipment (VNA, Oscilloscope, DMM, Probing)

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