Engineer Electrical Engineering

Maxime Descos

Francis Place, Chicago IL 312-***-**** ******.******@*****.***

linkedin.com/in/maximedescos/ github.com/maxislash Graduate student with a dual master degree in Electrical Engineering and Digital Systems Technology looking for a full-time engineer position

Skills

• C/C++

• VHDL

• Matlab/Octave

• Wireshark

• Cadence Virtuoso

• LaTeX

• FPGA Xilinx

• Arduino/Raspberry Pi

• Embedded Systems

• Xilinx ISE Design Suite

• Android Studio

• Isis Proteus

• AWS

Work Experience

01/2017 – 07/2017

Embedded Systems Engineer / Illinois Institute of

Technology, Chicago, USA

Developed an application for the Augmented Reality device of Microsoft, HoloLens to control a drone fleet. For that project, I studied User Interface in Augmented Reality Application and I developed an application using Unity to visualize a drone fleet. The app was composed of three different kind of map: the simple map using Google Maps API to display the drones according to their coordinates, the 3D map where 3D buildings where added to visualize the drones with the buildings in a normal environment and the real-time map, this map was modified in real-time by the data received from the drones’ sensors. 05/2016 – 09/2016

Hardware Engineer / Laboratory of Embedded Systems, Buenos Aires, Argentina

Designed a digital communication system using QAM modulation on Octave with Symbol Timing and Carrier Frequency Recovery. QAM is useful in digital communication because the quadrature carriers create a combination of phase-shift and amplitude-shift keying which is less subject to noise. The transmitter is composed of a QAM Mapper, pulse shaping, modulator and a sum block. The receiver is composed of a demodulator, low pass filter, symbol timing recovery block carrier frequency and phase recovery block and QAM demapper. The Symbol Timing Recovery was made using an Early/Late Symbol Recovery algorithm and the frequency and phase recovery used a Costas loop. The system is coded in Matlab/Octave.

2

05/2015 – 09/2015

Embedded Systems Engineer / Elocky, Bordeaux, France Built a smart and connected door lock prototype for a start-up, using Arduino and created the library needed for the sensors. The door lock was unlocked using an RFID card. A IMU was used to determine when someone was knocking on the door and send a notification to the user’s smartphone via the Raspberry gateway. Also, the IMU could detect intrusion depending on the force put on the door. The Arduino and the libraries created are coded in C/C++. You can find their website here: https://elocky.com/en/

05/2015 – 05/2016

Project Manager / Aquitaine Electronique Informatique, Bordeaux, France

Managed projects in several fields of engineering and customer relationships with different clients from small companies (bot for call centers) to the industrial conglomerate Thales (school social media app). With over 20 years of experience, Aquitaine Electronique Informatique made his name in Bordeaux region. We initiate and manage projects in Electronic, IT, Mathematics, Simulation or Telecommunications.

Education

2016- 2017

Master of Science in Digital Systems Technology / Illinois Institute of Technology, Chicago, USA / GPA: 3.87/4.0 Coursework: Embedded Systems • Computer Architecture • Real-Time Communications • Cloud Computing Technologies • Vulnerability Analysis & Control 2014 - 2017

Master of Science in Electrical Engineering / Bordeaux Institute of Technology, Bordeaux, France

Coursework: Digital Electronic • Computer Engineering • Programming • Signal & Image Processing • Circuits & Integrated Systems • Analog & Power Electronics • Automation & Control 2012 - 2014

Undergraduate Studies in Science/ CPGE Camille Jullian, Bordeaux, France

2-year intensive undergraduate program preparing for the competitive entrance examinations to French top-level "Grandes Écoles".

Main subjects: Mathematics, Physics and Chemistry. 3

Important Projects

Hardware Design Engineer / Illinois Institute of

Technology, Chicago

Developed three branch predictors using local and global branch history in VHDL on ModelSim. In modern CPU, the processor needs to know where will go the branch to pipeline it and go faster. Hence, I designed in VHDL three different branch predictor. One using the results of the last two times of the branch studied. One using the results of the last four times. And one using a global history register to demonstrate the behavior of one branches according to the other branches around it. I tried to test everything methodically. First a mathematical theoretical analyze was see what was the theoretical limit to achieve. After every block was tested and finally different algorithms with different loops or random behavior were used to compare all the predictors.

FPGA Engineer / Bordeaux Institute of Technology,

Bordeaux

Designed and implemented an 8-bit processor on a Xilinx FPGA in VHDL on Xilinx ISE Design Suite. The goal was to assemble combinatory and sequential functions to realize a programmable processor with a reduced instruction set (4 instructions: NOR, ADD, STORE and JUMP). The processor uses one operator, one operand (memory address) and an accumulator to make the instruction. The architecture is Von Neumann and the control unit is a Finite State Machine with 7 states. The processor was tested using a highest common factor algorithm and on a Xilinx Nexys4 FPGA board. Hardware Engineer / Bordeaux Institute of Technology, Bordeaux

Created a 3D Scanner using a LiDAR driven by an Arduino, a LUA program to transfer the data and C++ to reproduce the 3D scene. A LiDAR is a laser technology used to measure distance precisely and rapidly. With this sensor, I printed in 3D a turret and made it mobile by using servomotors and an Arduino. The turret is placed in a room and when the program is launched it will rotate to map the room. The data were send to the computer using a LUA program and finally the data were used to reconstruct the room in 3D with the library OpenGL.

FPGA Engineer / Bordeaux Institute of Technology,

Bordeaux

Realization of a maze game on FPGA using VHDL on Xilinx ISE Design Suite. The user used the four buttons of the Xilinx Nexys4 FPGA board to control the game. A debounce filter was implemented on all the buttons. Then the system checks if the movement was possible (no collision with a wall) then if yes, the RAM were the VGA controller take its data was updated. The 48 cells maze was generated using a recursive backtracker algorithm and a random number generator composed of XOR gates and shift registers.

Languages

French: Mother tongue

English: Fluent IELTS: 8.0 TOEIC: 980

Spanish: Good working knowledge

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