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FPGA ASIC RTL

Location:
Bellevue, WA
Posted:
September 22, 2017

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Resume:

SEOK HEE HONG

*** - *** - **** ac2fjz@r.postjobfree.com Sammamish WA, 98074

EMPLOYMENT

Chief Research Engineer UniTest Inc. Apr. 2015 - Nov.2016

Designed FPGA for LPDDR3 Memory Test System

Improved function that can be tested LPDDR3 memory up to 2Gbps.

Implemented timing calibration, test pattern generation, and pattern compare logics for LPDDR3 memory using FPGA.

Designed and verified with Verilog-HDL.

Verified FPGA in JIG board level and system level.

Supplied to SK Hynix Inc. priced about $0.8 million per unit which is currently used for mass production with 99.8% average yield.

Worked as a team leader to deliver product in a timely manner. Senior Research Engineer Samsung Electronics Co., Ltd. Mar. 2001 - Aug. 2014

Designed Modem for LTE System

Developed high speed serial interface that transfer data up to 5Gbps based on CPRI standard which connects the modem and the RF module.

Implemented as ASIC with 45nm UMC process.

Designed and verified with Verilog-HDL.

Tested ASIC in JIG board level.

Worked with “Faraday Technology (Taiwan)” in backend process.

Generated Tx/Rx channel test patterns for ATPG.

Provided to the world’s wireless communication service providers.

Designed Modem for WCDMA(HSPA), WiBro, CDMA System

All Modems participated in development were used in commercial systems.

Designed Tx Channels and implemented using PicoChip device on WCDMA(HSPA) project. Coded and verified with Assembly and C language

Designed Tx Channels and implemented using Xilinx Virtex4 FPGA on WiBro project. Coded and verified with Verilog-HDL

Designed Modem Test logics and implemented using Altera FPGA on CDMA project. Coded and verified with VHDL

SKILLS

Languages: Verilog-HDL, VHDL, and Assembly

ASIC Utilities: NC Sim, Debussy, Design Compiler, Prime Time, and Formality

FPGA Utilities: Xilinx ISE / Vivado and Altera Quartus

FPGA device: Xilinx Kintex UltraScale, Vertex 4, and Altera device

Debug Tool: ChipScope

EDUCATION

Education for Adults, Jan.2017~current, Cascadia College, Bothell WA

Preparing for Work, Jan. 2017~ Mar. 2017, Bellevue College, Bellevue WA

Master of Engineering in Electrical and Computer Engineering, 2001, Ajou University, South Korea

Bachelor of Science in Engineering, 1999, Ajou University, South Korea ADDITIONAL EXPERIENCE

Received a Six Sigma Black Belt certificate from Samsung Electronics, Co., Ltd., Nov. 2008.

Took charge of new employee training as an instructor at Samsung Electronics, Co., Ltd., Jan. 2003.

Visited the USA, Japan, and Taiwan for business trip and travelled more than twenty countries.



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