MOONISHA DHAMOTHARAN

408-***-**** • ac2dny@r.postjobfree.com

PROFESSIONAL SUMMARY

Expertise in VLSI Design and Verification with competent experience on ASIC IP.

Proficient in Verilog and System Verilog languages and UVM and OVM methodology for ASIC verification.

Experience in identifying test scenarios, verification, document preparation and code coverage.

Handled regression analysis, status tracking, debugging and timely bug reporting.

Converted Verilog test bench to UVM test bench.

Digital RFIC Design Simulation, Synthesis, Verification and testing using Verilog.

PCB Design and layout of Analog and Mixed signal circuits using Cadence, Kicad and Altium.

FPGA based design and programming using Xilinx ISE design suit.

Object oriented System Verilog principles using OVM and UVM methodologies.

Performed Physical verifications like DRC and LVS.

MS Word, Excel and PowerPoint.

Strong analytical and problem solving skills.

Self-motivated, Leadership Qualities yet teamwork oriented.

TECHNICAL SKILLS

Programming Language

Verilog, System Verilog, RTL, JAVA and SAS

Core Competencies

FPGA, ASIC, Xilinx ISE, Synopsys VCS, MATLAB, LabVIEW, Pspice, Python, Cadence Allegro, Kicad and Altium

Verification Methodologies

OVM, UVM

Lab Equipment

Oscilloscope, Function Generator, Signal Generator, Power Amplifier, Spectrum Analyzer and Logic Analyzer

PROFESSIONAL EXPERIENCE

Junior Hardware Verification Engineering February 2017 – August 2017

Ilmatic, San Francisco, CA

Top level functional verification and successful running of IO and Logic blocks.

Design and Integration of test bench Components, Assertions, Debugging and Regression analysis.

Designed and developed constrained random test cases in UVM and OVM

Developed Scoreboards for the IO blocks.

Wrote and executed verification test plans for both block and chip level.

Active involment in test case development and coding assertions.

Prepared test plans which includes various test cases to examine the behavior of the design.

Debugged RTL and Gate level simulations using simulators like simv and Synopsys VCS.

Ran gate level simulations with post layout timing information to verify timing

Logic Synthesis of RTL code developed using Synopsis Design Compiler.

Performed code coverage analysis.

Hardware Engineer Intern August 2016 – December 2016

Ilmatic, San Francisco, CA

Performed layout, logical, design, feasibility and electrical verification of circuit components.

Created a constrained random verification environment using System Verilog and UVM.

Functional verification with RTL and Gate level simulations.

Regression Analysis for design and assertion failures.

Designed and developed the schematic capture, layout checking, library creation, footprint and BOM generation for the wearable using Cadence Allegro, Kicad and Altium

Designed schematics for Bluetooth NFC payment reader compatible with Apple Pay, Samsung Pay.

Maintained and updated the symbols and footprint libraries for schematic and PCB design tools.

Included secure elements to keep our credit and debit card details protected.

Performed Design Verification, Validation and testing as required.

Managed multiple projects and improved quality of the product.

Graduate Student Teaching Assistant September 2015 – December 2016

California State University, Sacramento, CA

Worked with approximately 40 students weekly to help them achieve understanding and utilization of math concepts at all level.

Taught concepts from all levels of mathematics including Algebra I and II, Geometry, Trigonometry and Graphing.

Evaluated students learning styles and helped them prepare for upcoming exams after school or during study time.

Wrote progress notes and filled out time sheets after each session on weekly basic.

EDUCATION

Master of Science in Electrical Engineering December 2016

California State University, Sacramento, CA GPA: 3.47

Bachelor of Engineering in Electronics and Communication May 2014

Avinashilingam University, Coimbatore, India CGPA: 8.2

ACHEDEMIC PROJECTS

Double Precision Floating Point Adder/Subtractor

Designed and simulated Floating point Adder/Subtractor using Verilog in IEEE-754 format. Implemented a 64-bit binary adder/subtractor, shifter and a leading zero counter which was needed for the 64-bit floating point operation.

Pipelined Floating Point Vector Multiplier

Designed, simulated and synthesized a pipelined floating point vector multiplier using Verilog. A 32-element vectors A and B are multiplied element by element and the product is stored in vector C. Elements of A and B are 32-bit single precision floating point number expressed in IEEE 754 format. Performed code coverage and functional coverage.

Keypad door lock system

Designed and verified the digital logic using Verilog with 11 keys (0 – 9, LOCK key). The opening sequence is a 4-digit key combination and a master reset combination designed to reset the lock and bring it back to normal operation.

Static Timing Analysis

Designed an ALU using Verilog and tested it using Perl script. Analyzed the design by writing TCL scripts with constraints. Optimized a given netlist, generated area & timing report in design vision, checked for hold & setup slack.

Control Logic and Counter for a 6-bit Dual-Slope Analog-to-Digital Converter (ADC) in 0.18µm CMOS

Designed, simulated and finalized with layout. Designed each logic gate for its transient performance and various parameters like mid-point voltage, rise time and fall time were calculated. Simulated Front-end Design and Implemented Back-end Design layout using Virtuoso. DRC and LVS test was performed to identify the errors.

Binary Combinational Array Multiplier Design, Sequential Multiplier Design and LCD Interfacing

Designed the hierarchical design strategy using Verilog Hardware Description Language. Designed and simulated the array combinational multiplier algorithm and sequential shift/add multiplication algorithm using Verilog code.

HONORS and ACTIVITIES

Awarded first class with distinction at Avinashilingam Institution.

Member of the Rotary Club.

Chairperson of the Institute of Engineering and Telecommunication (IETE)

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