Engineer Project Management

DAWIT SOLOMON

**********@*****.*** (***) ***–**** Gilbert, AZ

Microelectronics Package Engineer: INTEL CORPORATION, Chandler, AZ. 2000-2016

Package Architecture Definition Characterization Pathfinding Development & Manufacturing

Project Management & Technology Transfer Methodologies New Product INTRODUCTION (NPI) Yield Improvement Strategic Technology Planning Metrology Tool Matching SPC FMEA JEDEC DFM

Successfully Completed Projects/Programs

Microelectronics Package Architecture Definition - New Product INTRODUCTION (INTEL CORP)

Led package definitions and designs adhering to performance, cost and schedule targets for a variety of INTEL product segments such as INTEL’s CPUs (2), Discrete Graphics (1), Embedded (IOT) (2), Servers (1), Communication (8) and Memory Products (2), SiP Pathfinding and stack-up recommendations

oAwarded Six Divisional Recognitions that recognized his contributions to packaging in the areas of process, package development, die/package/board co-design and low cost package design solutions that delivered significant cost savings to product teams.

Cost Reduction / Yield Enhancement: (INTEL CORP)

oPerformed feasibility studies that included cost/tool savings vs. Finish Flows to show that lower cost Finish flows require hard rejects that cannot be achieved using current CPU and Chipset reject classification models. Drafted and successfully ratified pilot strategy on low cost products.

oAligned all stakeholders on flatten ball (damaged ball) inspection losses (1700 defect per million) and closed in Quality Management Review Committee a strategy to relax criteria thereby reducing yield losses associated with “flatten balls”.

Strategic Technology Planning and Integration (INTEL CORP)

Package Technology Development Liaison to Business Units, engaged with divisional strategic product and marketing teams, identified key product technology drivers, inflection points and translated them into packaging demands to be used by packaging path finding teams to develop next generation package solutions. Published Product and Market Segment Requirements. Led device and package technology alignments for 10+ products through INTEL Product and Package Development and Planning Forums.

Manufacturing, Technology Transfer and Metrology (INTEL CORP)

Owned automated defect inspection recipe development, qualification, training and process transfer to offshore factories and engage through HVM ramp.

oAwarded two Divisional recognitions that recognized for his outstanding contribution to automate final visual inspection and eliminating manual final visual Inspection.

Microelectronics Package Performance Characterization (Thermal and Electrical)

@ Hana Technologies, Olin Interconnect Technologies and Polycon Corporation

Key customer interface with respect to package design and package performance requirements.

Setup and qualified electrical and thermal characterization laboratory

Published Company’s Package Thermal and Electrical Performance Handbook

Hardware/Software Skills Tool Owner: 3D X-Ray Tool, Automatic Visual Inspection System, Machine Vision Systems (MVS), Semiconductor Device Analyzer, Agilent Vector Network Analyzer (VNA)

FEA: COSMOS/M, AutoCAD, Cadence APD, JMP (Statistical Software)

Professional Memberships Institute of Electrical and Electronics Engineers (IEEE)

Components, Packaging, and Manufacturing Technology Society (CPMT)

Project Management Institute (PMI)

Author of multiple publications 9 total at ECTC, Semiconductor Packaging Symposium, 1st International Conference on Multichip Modules, a patent and 4 IPs (IP.com) relevant to electronics packaging.

EDUCATION

MS, Physics, ARIZONA STATE UNIVERSITY

MSE, Electrical Engineering, ARIZONA STATE UNIVERSITY

BS, Physics, AMERICAN UNIVERSITY in Cairo, Egypt

DETAILED PROFESSIONAL EXPERIENCE Page 2 of 2

Private Business Development: Land development for use of Wind Turbines outside Joseph City, Arizona (06/2016 – 04/17)

INTEL CORPORATION, Chandler, AZ 2000–2016

Package R&D Engineer/Platform Lead for Tablet, Smartphones and CPUs (03/2010–04/15/2016)

Tool Development / Tool Owner: 3D X-Ray for Server Product defect detection and metrology data collection.

Led automated inspection recipe development, qualification, training and transfer of Tablet, Smartphones and 32/22 nm (Tick/Tock) Client CPU products to offshore factories.

Divisional Recognition Award “Outstanding work to Automate Final Visual Inspection technology breakthroughs and enabling removal of Manual Final Visual Inspection.”

Divisional Recognition Award “Replacement of Topside Manual Final Visual with an automated visual inspection process with PCS in A/T process flows for all 32/22nm lidded (IHS) products.”

Embedded Computing Group: CPU Package Integrator/Package Definition. (06/2009–02/2010)

Led package development and tape-out of Sandy Bridge (32nm) 4 Core silicon on 2 Core scalable BGA footprint that enabled scalability and forward compatibility of Sandy Bridge and future Ivy Bridge (22nm) products for Embedded Computer Group customers.

Divisional Recognition Award “In Recognition of Results Orientation for the development of a Sandy Bridge (32 nm) 4C/2C BGA package design compatible with future Ivy Bridge (22 nm) requirements.”

Divisional Recognition Award “Completing the technical feasibility of a single scalable BGA Package for 4C and 2C Low power Sandy Bridge (32 nm) SKUs for ECG Customers.”

Mobility and Desktop Group: CPU Package Integrator/Package Definition (04/2007–05/2009)

Led cross-functional silicon, package and board team into defining packages for 45nm CPU (WFD-M), Graphics Processing Units (Larrabee 1P & 2), and 32 nm Server (Jaketown) product. Delivered low cost WFD-M 4L package with $72M cost savings. Completed feasibility study for Larrabee 1P that resulted in smaller form factor with $1.15/unit cost savings and $1.7M savings in development cost to Graphics Division. Drove adoption of L-shaped memory interface placement on Larrabee 2 die and package that enabled adoption of Larrabee 2 for Mobile MXM card applications.

Divisional Recognition Award “Using mobile system data and customer feedback, team tenaciously drove the Larrabee 2 team to support L-shaped local memory in the die quadrating and packages”

Divisional Recognition Award “Outstanding risk taking and successful delivery of lower cost 45nm (WFD-CPU) 4L package substrate to enable cost saving of $72M.”

INTEL Flash Product Group: Design Integrator Path Finding Platform (08/2006–03/2007)

Delivered TV definition, design and data collection of stacked die packages. Led cross functional team to implement enhanced and low-cost substrate design rules. Delivered feasibility studies for an 8 NAND die stack package for external customer that included completed Technical Risk Assessment and subcontractor assembler recommendation and transferred to development team for implementation.

INTEL Assembly/Test: Lead Integrator for external memory for SiP applications (07/2005–07/2006)

Oversaw packaging support with emphasis on understanding effects of package stress on critical transistor parameters. Recommended optimum package architecture and silicon/package design rules for system in package applications using DRAM. Defined test vehicle, and coordinated all sample builds. Assisted in wafer level testing using semiconductor device analyzer.

INTEL Assembly and Test: Customer Strategic Technology Integration Team (03/03–06/05)

Business Segment Integrator Wireless, Handheld, Mobile and Desktop Chipsets Group

Served as Package Technology Development Liaison to business units, engaged with divisional strategic product and marketing team. Identified key product technology drivers, inflection points and translated them into packaging demands to be used by packaging path finding teams to develop next generation package solutions. Led device and package technology alignments for 10+ products through Divisional and INTEL Package Development and planning forums. Oversaw Wi-Fi Radio and MAC package down selection and product/package alignment.

Published chipsets, wireless and handheld product segment requirements to drive INTEL’s package technology development efforts.

Published (@IP.com) four new packaging schemes using existing manufacturing technology:

Intel Communications Group: Partitioning Engineer (10/2000–02/2003)

Served as Package Technical Liaison to business project teams. Performed feasibility analysis and led partitioning analysis that determined highest performance technology solutions at lowest overall cost. Identified and drove adoption Ultra BGA Package as leading candidate for devices with stringent thermal and electrical requirements which resulted in significant package cost savings. Led cross-functional team from package electrical, package design, thermal, power, system, buffer design and die floor planning for 10+ communication products to produce low risk technology recommendation.

Divisional Recognition Award “Calypso, contributing to success of Intel’s 1st Optical framer-mapper solution for OC-192.”

Divisional Recognition Award “Capilano Product, CTO Group Recognition Award for outstanding packaging

Development”

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