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Electrical Engineering Design

San Diego, California, United States
November 11, 2017

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Nilay Ajaykumar Shah • San Diego, CA 92126 • (972)***-**** • SUMMARY

Total 6+ years of experience where 2+ years of experience as an IC Design Engineer in mm-Wave/ RF Circuit Design, Analog Circuit Design, Digital Circuit Design, 4+ years of experience in Layout Design and 2 year of ASIC /RTL Design Experience.

Proficient with 65nm, 40nm, 45nm, 28nm, 20nm and 16nm FinFET technology

Effective communication skills and a team player, quick learner and “Can do attitude” with attention to details. EDUCATION

Southern Methodist University (Dallas, Texas) Grad Date: May2016 Masters in Electrical Engineering G.P.A:3.94/4.0

C-DAC, ACTS (Pune, Maharashtra) Grad Date: Feb2010 PG Diploma in VLSI Design Grade: A

Gujarat University (Ahmedabad, Gujarat) Grad Date: June2009 Bachelors in Electronics and Communication Engineering C.G.P.A: 3.77/4.0 PROFESSIONAL EXPERIENCE

Tensorcom (San Diego, California) 1+ years

RF IC Design Engineer Oct 2016 – Oct 2017

Working on mm-Wave (58 GHz-65 GHz Frequency) Full chip simulation & testing, Voltage Controlled Oscillator (VCO) Design, Phase Shifter Design, Transmitter & Receiver Base Band Circuits Design on 40nm and 16nm Technology and optimizing the chip testing algorithm.

Worked on one tapped out for mm-Wave WiGig SOC product.

Southern Methodist University (Dallas, Texas) 2 years

Master Thesis June 2015–May 2016

Worked on mm-Wave(60 GHz-77 GHz Frequency)Phase Shifter Circuit Design in 65nm Technology under Dr.Ping Gui and assisted by Dr.Sudipto Chakraborty.

Teacher Assistant Aug 2014 -May2016

Assisted students for "Semiconductor and Integrated Photonics Fundamental" courses under Dr.Gary Evans.

Lead a team of four TA's at SMU's clean room lab for Fabricating and Testing MOSFET on Silicon wafer for Semiconductor Device and Fabrication course under Dr.Gary Evans.

Tutored Undergraduate Level Electrical Engineering courses at Altshuler Learning Enhancement Center.

Graded "Semiconductor and Integrated Photonics Fundamental" courses under Dr.Gary Evans.

Graded "Circuit Analysis-1" course under Dr.John Fattaruso.

Broadcom Communication Technologies Pvt Ltd (Mumbai, Maharashtra) 3 years 6months

Engineer-IC Design July 2010 - Dec2013

Evolved physical verified bit-cell layout on Cadence(Virtuoso)for multi-port register file compiler macros in 16nm FinFET technology.

Responsible for delivering DRC/LVS, I/R dropped clean, power efficient multi-port register file compiler macros layout from scratch in 16nm FinFET and 28nm technology.

Built standard cell library layout in 16nm FinFET, 20nm, 28nm technology.

Established layout for clock buffer cell library, custom standard cell, custom macros and ESD protection structure in 28nm and 45nm technology.

Collaborated with teams in US and Singapore to successfully complete various projects in 28nm technology as a result Two of which have successfully been taped out. 2

Nilay Ajaykumar Shah • San Diego, CA 92126 • (972)***-**** • RELEVANT COURSES

Transistor Integrated Circuit, Advance Communication Circuits, Advanced VLSI Design & Lab, Semiconductor Device and Circuit, VLSI Algorithm, Semiconductor Device and Fabrication, Digital Systems Design, Advanced Fiber Optics, Semiconductor and Integrated Photonics Fundamental. TECHNICAL SKILLS

VLSI Design Tool : Virtuoso (Cadence), ADS, Spectre RF (Cadence), AFS, EMX, HFSS, NC-Verilog, Cadence Encounter, Quartus (Altera), Synopsys RTL Compiler, Laker, Micro Wind, Xilinx Vivado, ModelSim.

Programming Languages : VHDL, Verilog, C, System Verilog, Python. Computer Tool & OS : MATLAB, Windows, Linux, Waveguide. PROJECTS

Frequency Shift Keying Transceiver (Transistor Integrated Circuits). Designed a 2.4 GHz transmitter and receiver system for Frequency Shift Keying using Direct Modulation scheme in 130nm Technology using Voltage Controlled Oscillator (VCO) followed by Class-E Power Amplifier (PA), Low Noise Amplifier (LNA), Active-Down Conversion Mixer and Local Oscillator (LO) and Low Pass Filter (LPF).

Amplitude Shift Keying Modulator (Advanced Communication Circuits). Lead a team of two to deliver power efficient and DRC/LVS clean 2.4 GHz Amplitude Shift Keying modulation schematic and Layout in 180nm Technology.

CMOS Instrumentation Amplifier (Semiconductor Device and Circuit). Developed an Instrumentation Amplifier circuit which has high CMRR, low frequency noise, low frequency operation and low supply voltage as 0.6 volts in 130nm Technology.

Data path and Synchronous Controller Design (Digital System Design). Developed the Data path and Synchronous Controller Design using Verilog in Quartus Tool to achieve operating frequency above 70MHz for Newton-Raphson equation for finding reciprocal values of 8-bit unsigned numbers.

p-channel Enhancement-mode MOSFET Fabrication (Semiconductor Device and Fabrication). Successfully performed oxidation, photo-resist, lithography, diffusion, etching and metallization steps to fabricate, model and probe-test (Testing) the p-channel Enhancement-mode MOSFET on Silicon wafer. Also calculated thermal oxidation (dry and wet) thickness and diffusion depths.

Trigonometric Digital Calculator using Cordic Algorithm (AVLSI Design and Lab). Lead a team of three to successfully develop Power Efficient Trigonometric Digital Calculator using Cordic Algorithm using Verilog. As a part of the project, implemented RTL design by Synopsys Design Compiler and chip Layout by Cadence Encounter Place and Route tool.

Single Quantum Well Separate Confinement Heterostructure Semiconductor Laser (Fundamental of Integrated Photonics).

Designed a Single Quantum Well Heterostructure Semiconductor Laser using Waveguide software.

Universal Asynchronous Receiver and Transmitter (C-DAC). Lead a team of two to achieve area optimized universal asynchronous receiver and transmitter using VHDL.

High Angular Resolution for Absolute Angle & Incremental Angle Encoder Reader for Astronomy Telescope System (Physical Research Laboratory).

Developed a code for PCI Express card using C Language to obtain a 1" degree angular resolution.

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