Design Engineer System

ANDREY DIDENKO

Russia, Moscow, ******. Cell: +791********. Email: ******.*.*******@*****.***

Seeking for a challenging and rewarding position of a

Sr. Digital Design Engineer / SoC Architect

BUSINESS PROFILE:

Digital Design Engineer with 10 + years of experience in IP design and SoC architecture

Extensive practice in front-end design of complex IP-blocks including microarchitecture elaboration, specification writing, RTL-coding and testing

Strong skills in HDL RTL code writing for ASIC/FPGA implementations

Familiar with professional CAD tools and modern techniques & practices in the sphere

Practical knowledge of conventional PC I/O protocols including high-speed standards

Significant experience in system integration of 3-d party IPs

Excellent knowledge of AMBA protocols set

Awareness of SoC architecture design fundamentals and understanding of digital schemes implementation tradeoffs

Successful tape-outs of single-/multicore SoC architectures with multiple clock and power domains

Ability to find out and create custom solutions for system performance enhancements

SoC FPGA prototyping, adapting design for FPGA implementation

Valuable experience in debugging. Close cooperation with verification team engineers

INTERPERSONAL SKILLS:

Self-motivated, well-organized, dynamic and result-driven

Detail-oriented, able to schedule own workload and plan tasks

TECHNICAL SKILLS:

HDL: Verilog, System Verilog

Simulators: Synopsys VCS, Mentor Graphics ModelSim/QuestaSim

ASIC Tools: Synopsys Design Compiler

FPGA Tools: Altera Quartus, Xilinx Vivado, Synopsys Synplify, Synopsys Certify

Ptotocols: UART, PS/2, SPI, I2C, USB, PCI, PCIe, SRIO, MIL STD-1553, SD, USB,

Ethernet, MII, GMII, RGMII, AMBA APB, AHB, AXI3, AXI4

Version control: SVN, Git

Bug Tracking: Bugzilla, Redmine

WORK EXPERIENCE:

09.2015 – Present

Leading Design Engineer / SoC Architect at Tecon MT, Moscow

Played key role in the following projects:

-Multicore SoC for industrial applications with high level of robustness with

four CPU cores (RISC-V architecture), shared L2 cache, DDR3 memory controller, embedded four banks of on-chip SRAM and set of peripheral interfaces

-Microcontroller SoC for industrial real-time applications with CPU core (RISC-V architecture), embedded on-chip SRAM, Ethernet 1G, CAN, UART, SPI, I2C …

Defined architecture & microarchitecture of SoCs

Designed and debugged 1G Ethernet IP (MII, RGMII interfaces)

Worked out custom protocol of system interconnect with Network-on-Chip (NoC) structure. Developed NoC Router microarchitecture specification

Designed SRAM AXI4 Controller for memory banks access

Designed Clock Reset Unit for SoC’s domains synchronization control

Integrated Synopsys AXI Crossbar IP into design

06.2014 – 08.2015

Leader of FPGA group / SoC Architect at Baikal Electronics, Moscow

Was involved in the integration type project (mostly 3-rd party IPs):

-Multicore processor SoC for telecommunication tasks with two CPU cores (MIPS), shared L2 cache, DDR3 memory controller, PCIe Gen3, Ethernet 10G, SATA Gen3, USB2, low-speed interfaces

Participated in SoC microarchitecture elaboration

Designed system PMU (Power Management Unit) scheme

Supervised system integration and verification of PCIe Gen3 IP

Adapted SoC design for FPGA prototyping using Synopsys HAPS platform. Adaptation included: simplification of system synchronization scheme, design constraints definition (SDC, XDC), substitution of ASIC memories for FPGA primitives

Carried out iterative process of SoC design partitioning, implementation and debugging

Achieved stable prototype operation. Solved problems with DDR3 and SATA interfaces launching with the help of daughter cards

Succeeded in FPGA bare-metal testing and Linux startup before SoC was taped-out

06.2001 - 05.2014

From Graduate Design Engineer to Sr. Digital Design Engineer at MCST, Moscow

The main projects:

-Several generations of Northbridge and Southbridge chips for high performance systems

-Set of specialized FPGA-based daughter cards for system IO extensions

Elaborated proprietary protocol and designed two generations of link controller for interface between Northbridge (CPUs + MC) and Southbridge (Peripheral IO) chips.

While the first generation of link interface achieved 8 Gbps speed and was based on 8-lane parallel LVDS, the second generation increased link throughput to 80 Gbps with 16-lane PCIe Gen2 PHY. The designs were silicon-proven

Developed two generations of custom low-latency protocol and controllers for high-speed (up to 80 Gbps) inter-processor communication interface for multichip NUMA architecture. ASIC implementations were successful

Designed M2M communicational protocol and link controller with remote DMA feature support to speed up MPI performance in computer clusters. It was silicon proved.

Integrated Synopsys PCIe Gen1 Root Complex. Designed Transaction Layer logic to achieve more effective link throughput utilization

Engineered FPGA implementation of SRIO Gen2 interface controller. Designed Logic Layer functional block (IO and Message Passing specifications). Altera’s IP was integrated as a Physical Layer

Designed and debugged a set of interface controllers: USB1.1 (OHCI), SD, PS/2, UART, PCI-PCI Bridge, MIL-STD-1553

EDUCATION & TRAININGS:

2016 Doulos Training Courses. Intensive System Verilog & UVM

1999 – 2001 Master of Science in Applied Physics and Mathematics

Moscow Institute of Physics and Technology (MIPT), Moscow, Russia

1995 - 1999 Bachelor of Science in Applied Physics and Mathematics

Moscow Institute of Physics and Technology (MIPT), Moscow, Russia

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