Design Engineering
Resume:
Mugundhan P
Chinnapa garden,
Bangalore-560046.
E-mail: ac1vd7@r.postjobfree.com
Mobile: +91-906*******
Seeking an graduate level trainee in VLSI VERIFICATION with an organization of high repute.
PROFILE SUMMARY
B.tech in Electrical and Electronics Engineering from Prince Shri Venkateshwara Padmavathy Engineering College, Anna University, Chennai
Good understanding of ASIC and FPGA design flow
Extensive experience in writing RTL models in Verilog HDL and Test benches in System Verilog and UVM
Very good knowledge in verification methodologies
Experience in using industry standard EDA tools for the front-end design and verification
SCHOLASTIC
2015 B.tech in Electrical and Electronics Engineering from Prince Shri Venkateshwara Padmavathy Engineering College,Anna University,Chennai with 67%
2011 12th from Bharat Matric Higher Secondary School, Krishnagiri with 86%
2009 10th from Sri Sai Krishna Vidhya Giri Matriculation School, Krishnagiri with 76%
VLSI DOMAIN SKILS
HDL: Verilog
HVL: System Verilog
Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA
TB Methodology: UVM
Protocols: AXI, SPI
EDA Tool: Questasim and ISE
Domain: ASIC/FPGA front-end Design and Verification
Knowledge: RTL Coding, FSM based design, Simulation,
Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis, ABV- SVA
PROFESSIONAL QUALIFICATION
Sep 2015 – Feb 2016 Maven Silicon Certified Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Center, Bangalore.
Experience-6months internship in Maven Silicon.
VLSI PROJECTS
Router 1x3 – RTL design and Verification:
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Questasim and ISE
Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.
Responsibilities:
Architected the design
Implemented RTL using Verilog HDL.
Architected the class based verification environment using System Verilog
Verified the RTL model using System Verilog.
Generated functional and code coverage for the RTL verification sign-off
Synthesized the design.
SPI Controller Core - Verification:
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Questasim
Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.
Responsibilities:
Architected the class based verification environment in UVM
Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification sign-off.
Physical Coding Sublayer – RTL design:
HDL: Verilog
EDA Tools: Questasim and ISE
Description : The (PCS) is a networking protocol sublayer in the Fast Ethernet and 10 Gigabit Ethernet standards. It resides at the top of the physical layer (PHY), and provides an interface between the Physical Medium Attachment (PMA) sublayer and the Media Independent Interface (MII). It is responsible for data encoding/decoding.
Responsibilities:
Architected the design
Implemented RTL using Verilog HDL
Synthesized the design
AXI UVC - AMBA AXI4 Protocol Verification
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Rivera Pro
Description: The AMBA AXI protocol is targeted at high-performance, high-frequency system and includes a number of features that make it suitable for a high-speed submicron interconnects.AXI UVC is a configurable UVM based verification IP .It verifies the AXI protocol and generates the required functional coverage .
Responsibilities:
Architected the class based verification environment in UVM
Verified the protocol with single master single slave environment
Verified the UVC by connecting maters and slave back to back
Generated functional coverage for verification sign-off.
RESPONSIBILITY UNDERTAKEN
Representative of CRESCENT BLOOD DONORS (CBD) which is students initiated blood transfusion organization
Organized the National Level Symposium AMPTESOHM 2k14
SUMMARY OF SKILLS
Excellent communication skill
Positive attitude towards work
PERSONAL SNIPPETS
Date of Birth: Dec 15 1992.
Languages known: Tamil, English.
Declaration
I hereby declare that the information furnished above is true to the best of my knowledge.
DATE : Yours faithfully,
PLACE: (Mugundhan P)
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