Hanri Bouzari

*** ***** ***. ****** *: 469-***-****

Laramie, WY 82072 ac1n72@r.postjobfree.com

SUMMARY

Test Product Development and System Validation Engineer with over 18 years of experience in developing and integrating sub-micron SOC devices test programs production, characterization, yield enhancement, and test time reduction. Skilled in qualifying products through collaboration with team of Design, Product, DFT, Technology, QA, and yield enhancement engineering teams into high volume global semiconductor manufacturing sites.

TECHNICAL SKILLS

Credence Sapphire-ATE & TCU

Teradyne IGXL Ultra Flex, IPJ750

Advantest 93K-ATE

Agilent /Tektronix DSA-13GHz

CMOS Process technologies

Statistical Analysis, DOE, ANOVA

JMP, DataPower, Galaxy, MiniTab

Memory Process and IC fabrication

SPC, GR&R

C/C++, VB, Perl, Python

Lean Six Sigma Green Belt

Oscilloscope, Spectrum Analyzer

PROFESSIONAL EXPERIENCE:

Qualcomm Inc. – San Diego, California 3/2015– 9/2016

GPU Hardware – Post Silicon Validation Engineer – Contract

• Worked closely with Power Management team to debug and characterize a new current sensing of PMIC using adb

commands and bench mark vectors and Keysight Oscilloscope and Spectrum Analyzer.

• Post Silicon Debug- Evaluating GPU hang in VI OS-free environment by re-producing the state at hang

moment and using register, debug bus signals and debug tools such as scan dump and MISR through

Trace32 - Lauterbach JTAG debugger for further evaluation.

• Evaluated GPU hang state by creating binary dump, kernel log files in Android environment using ADB

commands in MTP- Modem Test Platform debug board.

• Executed and analyzed nightly or weekly regression runs to validate GPU blocks.

Intel Corp. - Austin, Texas 6/2013- 2/2014

System Validation Engineer- Contract

Expert in High Speed I/O - MIPI DSI Protocol and debug, including knowledge of relevant debug tools (MIPI protocol, scopes, logic analyzers, Chip Scope, D-CAT-DSI (Capture and Analysis Tool).

Executed MIPI DSI Protocol Conformance and D-PHY Compliance testing across different Process Levels for Intel’s upcoming Smart phone products.

Worked closed with other engineers to automate DSI tests on bench environment and analyzing the data.

Enabled MIPI DSI Protocol Conformance Test infrastructure by analyzing and help debugging various version of D-CAT (DSI Capture and Analysis Tool).

Advanced Micro Devices - AMD, Austin, Texas 1/2011- 8/2012

Product Development Engineer, ATaC (Advanced Test and Characterization) Functional Group - Contract

Developed test programs to bring up functional CPU core patterns for post silicon validation of next generation Multi-core CPUs/GPUs microprocessor package device on Credence – Sapphire ATE.

Implemented Functional Regression techniques to validate post silicon test patterns for worse case limiters.

Performed and analyzed functional CPU and GPU patterns limiters and found worse case speed paths in silicon debug using ATE to generate scan dump (RTL codes) files and also used LICAT -AMD’s laser tool in Failure Analysis to improve process performance margin considerably.

Developed Circuit Sensitivity- mini characterization ATE program flow in area of functional testing to eliminate engineering involvement.

Panavision Imaging, Homer, New York 9/2010- 1/2011

Test Engineer, CMOS Imaging Sensor -Contract

Developed final and wafer level test programs for CMOS Imaging Sensor –DLIS 2K on Teradyne – IP750

Published Test Program Overview and Preliminary test strategies to provide low cost and effective solutions for high volume manufacturing for PE Department.

Developed and debugging functional test patterns for yield enhancement activities and collaborate closely with design team for new pattern generation in final test program.

Designed probe needle card and Probe Interface Board for TSK Prober.

Freescale Semiconductor, Austin, Texas 5/2004 – 12/2009

Test Engineer, Networking and Multimedia Group

Integrated and sustained final test program to market POWERQUICC- PQ38K Network Processor device on ATE - Teradyne UltraFlex tester.

Integrated pre-qualification test program on ATE from a team of 5 engineers and releasing test programs to Test and Product Engineer team in offshore foundry site.

Developed and summarized characterization test suite Local Bus AC specs.

Implemented new sets of scan, jtag, and fused patterns for PQ38K Chartered test program.

Analyzed characterization data for FMAX, VDDMIN search with JMP.

Identified root cause of a process shift in pre-qualification HTOL reliability stress test failure by implementing various characterization technique and shmoo plots.

Test / Product Engineer, Cellular Products Group

Developed and maintained wafer level and final test programs to market LTE2 mixed signal wireless/baseband processor on Verigy 93K.

Conducted weekly conference calls to TSMC & UMC PE/TE team for executing test programs transfer and ramp up.

Improved scan yield for ATMC and UMC wafer probe by 5%, working with Verigy Application Engineer and DFT team to develop additional engineering probe insertion.

Conducted process window split sample characterization and completed statistical analysis of marginal data with Minitab.

Maxim Integrated Products, Dallas, Texas 11/2000-12/2002

Test Product Engineer II

Developed, modified and debugged mixed signal T1 Transceiver device silicon and final test programs on ATE – Teradyne Catalyst tester.

Characterized PLL of new products on bench test and correlated to ATE test program for production release.

Conducted yield enhancement, test time and cost reductions, achieving the initial objectives of projects.

Converted test programs from one test platform to different test platform.

Transferred and correlated test programs to offshore foundry site.

Monitored production cumulative yield trends and improved yield flows.

IBM Microelectronics Corp, Essex Junction, Vermont 5/1996 –11/2000

Senior Associate Product Engineer

Established engineering and scientific analysis on problems such as fail signature analysis; coordinated physical failure analysis, and correlating fail modes and defects to process sector, in collaboration with DRAM Development Alliance-(IBM/IFX/Toshiba).

Provided direction and assisted manufacturing in achieving programs productivity by monitoring module yield learning, parametric test data analysis and yield support with SAS.

Monitored 256Mbit SDRAM cumulative module yield resulting and improved fab baseline defects and yield performance.

Investigated relevant trends in DC parametric versus in line measurement trends.

Conducted fail corner signature analysis and correlated to In-Line measurements for low yield memory products.

Provided bit fail map analysis for physical failure analysis team.

Associate Product Engineer

Analyzed data for Process Window tests on new 16Mbit SDRAM designs with statistics software.

Tested, debugged and modified memory products utilizing the Teradyne J997 Memory Tester.

Provided the necessary data analysis for the quality and reliability team’s 16Mbit SDRAM and stacked memory functional testing.

Compared other vendor SDRAM specifications, ensuring IBM memory products exceeded current market specifications.

EDUCATION:

Purdue University, West Lafayette, Indiana

Lean Six Sigma Green Belt Certification – July 2011

Arizona State University, Tempe, Arizona

Master of Science in Electrical Engineering Technology – August 1995

Scholarships:

Arizona State University Graduate College – Magna Cum Laude, The Engineering Honor Society -Tau Beta Pi

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