Mark Harriman

Director of M.J. HARRIMAN LIMITED

Area of Interest: Electronic Engineering, FPGA technology, Digital/Analogue Electronics, Audio/Video Technology.

Permanent Address:

* **** *****

Lincoln, Lincolnshire,

LN6 0RD

Mobile: 077********

e-mail address

ac1n4f@r.postjobfree.com

Objective: Contribute significantly to innovation in the form of groundbreaking products, publications and contribution to knowledge. Develop skills to target key areas of the market in terms of both employer and customer requirements. Progress and develop a business in order meet the requirements of all available potential markets and outstrip competitor capability in those markets. Lead and contribute as part of a team meeting deliverables effectively, efficiently, on-time, within budget and where possible exceed customer expectations. Work with leading companies that are committed towards the development of cutting edge products for a strong expanding application base. Core skill sets in this CV can be divided into three discrete groups: Electronics Engineering, Software Engineering and Management.

Baseline Cleared: Ferranti Technologies, Oldham, Lancashire.

Work and Education:

Rivertrace Engineering, Unit P/Kingsfield Business Centre/Philanthropic Rd, Redhill RH1 4DP. Employed as a Contractor (March 13th 2017 – April 7th 2017) (Core skills: Electronics/Software Engineering)

FOCON-LUMINATOR GROUP, Damvang 2, 6400 Sønderborg, Denmark, 2017. Employed as a Contractor (February 7th 2017 – February 21st 2017) (Core skills: Electronics/Software Engineering)

Ziztel Limited, Arnold, Nottingham, Nottinghamshire. Employed as a Contractor (December 14th 2016 – December 17th 2016) (Core skills: Electronics/Software Engineering)

Ferranti Technologies, Oldham, Lancashire. Employed at a Contractor (April 4th 2016 – April 22nd 2016) (Core skills: Electronics Engineering)

Nexeon Limited, Abingdon, Oxford. Employed at a Contractor (March 7th 2016 – 09/03/2016) (Core skills: MATLAB, Microsoft Visual Basic and .NET)

PRP Optoelectronics, Swindon, Employed as a Contractor (January 14th 2015 – June 16th 2015) (Core skills: Electronics Engineering and Software Engineering)

J+S Limited, Barnstaple Employed as a Contractor (August 18th 2014 – October 22nd 2014) (Core skills: Electronics Engineering and Software Engineering)

Thales, Manor Royal, Crawley Employed as a Contractor (June 2nd 2014 – August 7th 2014) (Core skills: Electronics Engineering and Software Engineering)

Alstom, Stafford, St Leonards Site, PES, Controls Group Employed as a Contractor (August 12th 2013 – May 30th 2014 ) (Core skills: Electronics Engineering and Management)

GE Aviation Bishops Cleeve Employed as a Contractor (February 5th – July 22nd 2013) (Core skills: Electronics Engineering and Software Engineering)

BARTEC VODEC Ltd. Employed as a Design Engineer (January 27th 2010

January 30th 2013)

BARTEC VODEC Ltd., No 5 Centurion Business Park, Dabell Avenue,

Blenheim Industrial Estate, Nottingham, NG6 8WA. (Core skills: Electronics Engineering and Software Engineering)

TRW-Conekt Employed as a Contractor (September 15th 2009 – November 10th

2009).

TRW-Conekt, Technical Centre, Stratford Road, Shirley, Solihull, B90 4GW. (Core skills: Electronics Engineering)

Registered for PhD Studentship in Mechatronics (October 2002 – September

2008)

Loughborough University, UK (Core skills: Electronics Engineering and Software Engineering)

Master of Engineering in Electronic Engineering, (September 1998 – July 2002)

University of Manchester, UK (2.1) (Core skills: Electronics Engineering, and Software Engineering)

Advanced GNVQ in Engineering (September 1995 – July 1997)

Grimsby College, UK (Distinction) (Core skills: Electronics Engineering and Software Engineering)

City and Guilds Electronic Servicing Part 2 (September 1997 – July 1998)

Grimsby College, UK (Distinction) (Core skills: Electronics Engineering and Software Engineering)

City and Guilds Electronic Servicing Part 1 (September 1994 – July 1995)

Grimsby College, UK (Distinction) (Core skills: Electronics Engineering and Software Engineering)

Industrial Experience:

Most relevant knowledge and experience:-

Code Porting Project. Although this is not data transform it does demonstrate my skills at converting a project from one coding format to another. I had a case in the summer of 2015 whereby I required an RS232 transceiver in order to provide two communication between an piece of VHDL code running on a development board and a PC. I did find a suitable piece RS232 transceiver but the code was written in verilog and therefore would not be compatible with my VHDL project. I therefore set about the task of creating a VHDL version of the Verilog also I created test benches for both pieces of code in the respective languages of VHDL and Verilog respectively. The result was a complete a complete porting of the Verilog RS232 transceiver into VHDL allowing the module to be both parameterised for the context of use and initiated directly into a VHDL project.

Knowledge of XSD, XLS and XML. Gleaned from researching publications on the various implementations and standards.

UI Development. Experience developing applications that have a sophisticated user interface on multiple platforms including Microsoft Visual Studio, Android Studio and National Instruments LabVIEW.

Android Application Development: Developed a series of applications with Android

Studio to work in conjunction with the Sensor technologies present on mobile phones including: GPS, Gyroscope and Accelerometer. The UI for these applications were written in XML.

In this section the skills that were critical and utilised for the particular roles are stated.

Rivertrace Engineering: Electronics and Software Engineering (March 13th 2017 – April 7th 2017)

(Core skills: Electronics and Software Engineering)

Main project involved redesigning a PFM/ORB PCB board used for the measurement of oil, gas

and solid particles in water. Redesigning work involved reviewing existing design, surveying

aspects of other companies technologies, designing a new LED current driver circuit and

redevelopment of the Lattice Semiconductor FPGA Firmware. Performed a design change on a

Horner PLC using Cscape.

Focon-Luminator Group: Software Engineering (February 7th 2017 – February 21st 2017)

(Core skills: Software Engineering)

Project was concerned with supplying a review and estimate for upgrading a Rail Information System for a new set of customer requirements. Performed impact analysis to detail which software applications would need updating and what coding updates need to be actioned in order to complete the updates. Outcome of the above was a detailed work plan that included a estimations for both the upgrade in total and how long each work package was expected to take.

Ziztel Limited: Electronics/Software Engineering (December 14th 2016 – December 17th 2016)

(Core skills: Electronics/Software Engineering)

DO254/IEC Compliant VHDL Designs (Implementation) and Testbenches (Verification) for

Bespoke Public Address and Loud Speaker / Telecommunication Systems. Resolved issues

involving the both the practices of archiving new projects and retrieving the archives of old

projects. Schematic and Layout Design of Mixed Signal PCB Designs containing Analogue and

Digital IC including CPLD/FPGA/DSP devices and interfaces to external “credit card” PC's

including Raspberry Pi and Beaglebone Black. DO254/IEC Compliant VHDL designs targeting

implementation on FPGA Devices. Documentation production consisted of reports to

Directorship / Management transmitted by email outline the actions that have been taken and the

results that have been achieved.

Ferranti Technologies: Electronics Engineering (April 1st 2016 – April 22nd 2016)

(Core skills: Electronics Engineering)

Documentation Production to write the FPGA/CPLD section of the System Development Plan working with the Directorship / Senior Management. This involves working across the entire development cycle of FPGA/CPLD based designs. This work is based on IEC61513 and IEC60987 instead of DO-254 as this is a non-aviation based Defense Application. The completed report outlined the roles and responsibilities of four FPGA Engineer, included visual aids showing the processes and was compliant with the IEC documents cited above.

Nexeon Limited: Software Engineer (March 7th 2016 – March 9th 2016)

(Core skills: MATLAB, Microsoft Visual Basic and .NET)

Project was to produce a piece of software which automates the process of performing a data transform task. The data transform involved the conversion of the companies existing research data (which was the Silicon Structure in the anodes of Lithium-ion “coin cells”) contained in MATLAB Workspace format into a customised DOS based file system containing the tab separated “research data” text files on the appropriate paths therefore making the data accessible on the server using their database. The core code to produce the database accessible structure was written in MATLAB. Microsoft Visual Basic and .NET constructs are used in MATLAB with GUI allowing for rapid generation user defined spreadsheets formatted for report production and experimental data comparisons. The MATLAB code that produced was peer reviewed and handed over to the Production Director / Management / Senior IT Staff for the dual purpose of demonstrating how the code worked and also how/where it could be modified to include additional code for other purposes.

PRP Optoelectronics Limited: Electronics Engineer (January 14th 2015 – June 16th 2015)

(Core skills: Electronics Engineering and Software Engineering)

The project I was working on involved the calibration of LED arrays. The apparatus used for this task consisted of a light measurement device mounted beneath the LED array on a computer controlled stage. The light measurement device was a Pin-10 diode the output of which is fed into a Video Amplifier then into a Digital Multimeter (DMM) which in turn networked to a PC allowing Data Acquisition to be performed. The computer controlled stage also interfaced with the PC over Ethernet. All three devices (LED array, DMM and stage) are then interfaced to and controlled by a PC running Microsoft Visual Studio 2013.

Interfacing with Clients / Senior Management / Directorship: the purpose of this was not only outline the intent of Engineering activities but also to convey the steps taken to address them.

Embedded C/C++: One of PRP's existing products was a two dimension LED array intended to be used as a gun sight and based around a PIC Microcontroller. The previous build of code had two functional aspects that were being controlled by a single parameter: refresh rate and display brightness. I was tasked with reverse engineering and redesigning the code so that both these functions could be controlled independently e.g. mutually exclusive parameter sets. The first step in this process was to product a specification for the code and this involved reverse engineering the code to discover both the architecture of the code, timings and waveforms and also where possible the block diagrams.

C#, C/C++ and .NET: Most of the recent Applications developed at PRP were created using C# with the .NET software framework. This followed on from choosing Microsoft Visual Studio 2013 as the main software development platform moving forward after the initial work before more was developed using Visual Basic 6 (more detail below on this). The purpose of the developed Applications was to drive a test rig for the calibration of a one-dimensional LED array. The test rig consisted of three key elements: one-dimensional LED array, Single Pixel Camera and Camera Stage. All three key elements were networked using TCP/IP through a switch to a PC running the C#/C/C NET Microsoft Visual Studio 2013 Application and in addition the stage was controlled used as a set of Dynamic Link Libraries (DLLs). One of the objectives of the application was to harvest the radiometric values of the every LED in the array and store the results to file. This involved spatially calibrating the position of the Camera Stage and ultimately the Single Pixel Camera so that its position would align to the centre of its radiometric field of any LED requested. The radiometric values from each individual LED were harvested by cascading the Single Pixel Camera with a Video Amplifier with a Multimeter operating as a data acquisition unit. Each LED's radiometric values were sampled only once and the entire sample set of this experiment saved to a spreadsheet compatible file for later analysis. This work formed the input to calibration algorithm as it gave the initial Radiometric Profile of the one-dimensional LED array.

Microsoft Visual Studio 2013: The company has a legacy of applications developed using Microsoft products including: Microsoft Visual Basic 6 and Microsoft Visual Studio 2008. Therefore the latest version of the development suite which is Microsoft Visual Studio 2013 was chosen.

Visual Basic 6: Legacy applications going back as far as 1998 required support so it was essential to use Microsoft Visual Basic 6 to modify application behaviours. The reason for this is two-fold Microsoft Visual Studio 2013 is not backwards compatible with Microsoft Visual Basic 6 and a lot of the PC's in the companies date back to the 1990's and early 2000's therefore there maybe compatibility issues with the file output of Microsoft Visual Studio 2013.

CSharp: Nominated as the language of choice as this was consistent with developments made to date by other parties.

J+S Limited: Firmware Engineer (August 18th 2014 – October 22nd 2014)

(Core skills: Electronics Engineering and Software Engineering)

Multifunction PCB card was developed which utilised an Altera Cyclone V FPGA. This involved first the designing of the PCB schematic and layout using Altium Designer and Microsoft VSIO. The Altera Cyclone Design was carried out using Altera Quartus II 13.1 using a system on a chip (SOC) design created in Qsys that contains an instance of the SoftCore Nios II processor. Eclipse IDE was used to create the embedded C/C++ software to drive the Nios II processor and via which the wider architecture.

Documentation Production: PCB Design Schematics, MSVSIO prospective PCB layout, Quartus II FPGA Design, Qsys Design and C/C++ Source Code.

Peer Reviews: regular reviews of the present state of work of the project were undertaken for the purpose of both communicating the present direction of the production and proposing engineering changes as well as evaluating potential next steps.

Senior IT Interfacing: Interfaced to Senior IT staff for cases of PC usage in the context of development e.g. IP addresses and port usage.

Eclipse Suite: Software development environment for writing the C/C++ code targeting the Nios II processor.

Embedded C/C++ used for the creation of the code which utilises the resources listed in Qsys (more detail below) for the implementation of the System-on-a Chip (SoC) design. Developed a GUI for a Colour Touch Screen Display in C/C++ to replace an otherwise push button based front panel. The C/C++ code made use of higher-level libraries for driving the touch screen display. The GUI consisted of a structured layout which Graphically illustrated the configuration parameters being controlled rather than using a system of menu's driven through push button activity.

Altera FPGA: Altera Cyclone V FPGA devices were targeted for use as the demands relating to the speed and size of the design could be met by this family therefore medium and large scales Arria and Stratix FPGA devices were not required.

Quartus II 13.1: Vendor specific Design tool created for exclusive use with Altera CPLD/FPGA devices.

Qsys: SoC design tool used for producing a module for use in Quartus II that encapsulates all peripheral, memory, Microprocessor and port interfaces as well instantiating key resources such as 32 bit SoftCore Nios I/II Processors (32 bit Microcontroller/Microprocessor) and DSP processors.

Altium Designer: PCB design suite used to both correct and create the schematic designs throughout the course of the project.

Thales: Hardware Engineer (June 2nd 2014 – August 7th 2014)

(Core skills: Electronics Engineering and Software Engineering)

Worked as a member of a team on a complex multi-PCB system which utilised many Altera Arria FPGA and MAX 5 CPLD devices. My work on this particular project involved specifying and design the firmware for one of the Altera MAX 5 CPLD devices.

Eclipse Suite: Software development environment used for developing the C/C++ code ran on the Nios II processor.

Management / Documentation Production: Strong commenting and documentation skills demonstrated in this role including the generation of Function Requirements Specification (FRS) and Function Implementation Specification (FIS). FRS states what the requirements for the design are and the FIS states how they have been chosen to be met.

Mentor Graphics HDL Designer: Top level design tool allows for the instantiation of VHDL/Verilog modules and their signal flow to be defined on a common canvas.

Altera CPLD/FPGA: Altera MAX 5 CPLD's and Arria FPGA devices used as part of a complex design as these offer a good compromise between performance and cost.

Quartus II 13.1: Vendor specific Design tool created for exclusive use with Altera CPLD/FPGA devices.

Qsys: System-on-a-Chip design tool used for producing a module for use in Quartus II that encapsulates all peripheral, memory, Microprocessor and port interfaces as well instantiating key resources such as SoftCore Nios I/II Processors and DSP processors.

ALSTOM: Line Coordinator (August 12th 2013 – May 30th 2014)

(Core skills: Electronics Engineering and Management)

Worked at ALSTOM GRID LIMITED in Stafford in two main roles: Line Coordinator/Manager/Technical Lead and Firmware Engineer.

Management / Documentation Production: Gate Review 6 (GR6) reviews the documentation for the latest set of HVDC PCB cards in the Controls and Valves departments at ALSTOM GRID. GR6 addresses a series of questions organised under the headings of: Bill-of-Materials, PCB Blank, Production Test, First off Build, Sourcing, New Product Introduction, Hardware Design and Firmware Design. Questions can be answered with a N/A, YES or NO response. For the N/A and YES responses a tri-colour code is applied with colours: green meaning full supporting evidence, orange partial supporting evidence and red meaning no supporting evidence.

Peer reviewed: reviewed numerous pieces of documentation to examine the descriptions align to what has been achieved and documented in the Engineering fileset.

Senior IT Interfacing: Numerous setup issues with my PC needed to be addressed and also there were cases whereby the old Hard drives of former members of staff needed to extracted from the archives and the respective processes followed.

Aldec ALINT: There was a requirement for a particular product containing a Microsemi (formly Actel) FPGA Verilog code to be linted. A policy was created based on Verilog All policy. The results of running this policy against the Verilog code were such that there were in excess of 20,000 violations in scope of 135 rules.

GE Aviation: FPGA Developer / Documentation Work (February 5th 2013 – July 22nd 2013)

(Core skills: Electronics Engineering and Software Engineering)

Initially worked in the role of a Firmware Verification Engineer updating a testbench for a legacy product that required a design change. Also worked on a number of different products include one that required a test verification procedure to updated and another whereby I was required to check reports for errors.

Legacy Software Support: Reverse Engineered Product based Test Software with the intent of creating Verification Specification's as the original documentation for the code was either never produced or lost. The Verification Specification was then placed into the Companies Document management system for checking and approval. Once the Verification Specification was approved the next task could commence which was creating the Test Software using the companies latest C/C++ development environment.

Peer Reviews: all documentation work at GE was subject to documentation control which consisted of authoring, checking and approving documentation. Documentation was produced which not only addressed the requirements of the Engineering process but also directly the needs of the Business.

Senior IT Interfacing: Initial issues setting up the PC for the project as they needed to be configured properly to be compatible with the various builds of Firmware that were being developed.

Altera: Altera FPGA Devices were used as the basis for the project carried out at GE Aviation.

Altera Quartus II: This was used to edit and compile the VHDL code for both the implementation and (self-checking) testbenches.

Mentor Graphics ModelSim: Working as a Verification I had to both create and modify self-checking testbenches to suit the requirement set of the specific project I was working on. ModelSim was the tool of choice to Verify correct operation of the modified design with the modified testbench.

Documentation Production / Management: As a human resource firmware was not the only task I undertook throughout my time at GE I was also involved checking stage of their document management system in order to correct and verify prior to the rework. I was also involved with updating test documentation for updates to the companies legacy products.

BARTEC VODEC (January 27th 2010 – January 30th 2013)

(Core skills: Electronics Engineering and Software Engineering)

Worked in role of Senior Design and Development Engineer. The role involved developing new products as well as maintaining and performing design changes on older products. The company main focus was the Oil and Gas Industries over my time there this expanded to Nuclear, Military, Navy and also Hydro-electric Dams.

Management / Client facing / telephone conference meetings with customers: the purpose being to determine their requirements, advise on builds / technical aspects of proposed systems and also to review any future business opportunities.

Technical Lead on numerous high profile projects in order to determine how best to use existing resources and what resources need to be brought in, purchased or developed to meet current technical objectives.

Documentation Production: Hardware Requirements Specifications, Firmware Verification Test Specifications, PCB Verification Test Specifications and also the full commenting of code including block comments appearing at the top of the code describing the main function of the code and also the preamble comments that appear before any block of code or function and also a comment per each individual line of code.

Peer Reviews: All work was peer reviewed prior to engaging the use of external contractors including software developers, hardware developers and also PCB layout design.

Senior IT Interfacing: Numerous cases including setting up drive access, subversion server, Wifi access and transferring of content from older server to a new server.

Requirements Analysis: Reviewed specifications noting contradictions, omissions and surplus requirements.

Unit Testing: Performed on both VHDL modules and also finished production PCB boards in order to provide both confirmation of functionality and correct component build/PCB issues.

Integration Testing: when components are combined into higher level design constructs there exists a series of verification tests based on either complete coverage testing, user test cases or stories. This is done to provide a high level assurance that the code meets the derived requirements by verification.

Experience of Configuration/Release Management and Source Control Tools: Use of Tortoise SVN Subversion for version control both internally and externally releases.

Build tool chain experience: .NET for Visual Basic and Visual C/C++.

Public Address and General Alarm (PAGA) Systems: Designed and Modified PAGA Systems which consist of individual modules, some of which contain bespoke firmware, configured to individual customer requirements.

Microsemi (formly Actel) FPGA: Both Antifuse and Flash based FPGA devices were used. The former were one-time programmable devices designed for use in hazardous environments. The latter were reconfigurable and of larger capacity allowing for post-release customisations and the implementation of more complex designs.

Mentor Graphics ModelSim: Extensive use of ModelSim made for the Verification of both VHDL designs and VHDL modules using self-checking Testbenches based on User Defined Cases and Module Tests targeted for 100% test coverage.

Digital and Analogue Circuit Design: The PAGA Systems consisted of a single audio path commonly driven by both a Digitally generated signal and also by Analogue signal source much as a music system or microphone. Digital designs are implemented mainly in the FPGA firmware using synchronous logic designs designed in accordance with behaviours defined in the specification. Analogue circuit design is mainly concerned with the implementation of circuit designs that affect the audio path including audio amplifiers, BP/BS/HP/LP filters, compressor and in addition designs concerning power supply stages.

.NET C/C++/C# Microsoft Visual Studio Application Development. Applications ranged from Data Mining Tools to Alarm Tone Design, Combination Logic and Sequential Logic Generation. Also tools were designed to work in Conjunction with Mentor Graphics ModelSim to produce Force Files for previous FPGA firmware designs that could not be simulated. Applications were based on both Command Line and Windows Form.

OrCAD: PCB Design Suite used for updating the companies PCB schematics prior to release to PCB Design Engineer who has the responsibility for board layout.

LabVIEW: Used for the Verification Testing of CLASS Speaker System and PAGA front panel indication. The former CLASS Speaker System was developed for both remote testing of speakers and also presetting transformer coil tapping for Power Output Level using the Data-Aquisition LabVIEW tool set in order to provide a stimulus and read back digital data from the devices. The latter PAGA front panel indication was to provide a means of remotely monitoring the status of the PAGA system such as control panel, alarm, speaker line and total system failure modes.

TRW Conekt (September 15th 2009 – November 10th 2009)

(Core skills: Electronics Engineering)

TRW Conekt was a division of the TRW Technical Centre which specialised in the customisation of Automotive parts for very low volume runs e.g. they would take a gear box and transmission intended for 10,000 units of Vauxhall and adapt is to a run 20 “one offs” for an end client like Maclaren. Due to the Automotive work being quite light the company took on an Oil and Gas Project which was to locate the cause of a reset failure of a particular piece of rig and also once that was completed redesign the PCB. The end result of the research was that there were many design features that could of contributed to the reset condition but the exact cause could not be determined therefore the project could not be gated onto the next phase. More detail on the former analysis of possible causes is outlined in the sections that follow.

Documentation Production: Daily reports were issued to the line manager in order report present state of progress of the project, what results had been achieved and what future work was proposed.

Root Cause Analysis: Tasked to find the root cause of a reset failure on a multicard PCB system. This involved analysing the transient and steady state behaviour of the rig using an Oscilloscope and Digital Multimeter. Also the schematics and layout of the individual PCB cards were examined and in this particular case certain features were found in the multi-layered PCB: sparsely populated layers, non adjacent power and ground planes, signal lines running inbetween power and ground planes, excessive use of VIAs, excessive number of layers for the complexity of design and improperly finished tracks, VIAs, PADs and connector mounting points.

Electronic Circuit Design: I was also deployed to examine one of the existing Electronic Circuit Designs to justify why it was not operating as intended and recommend modifications.

Mechatronics Research Group (October 2002 – September 2008)

(Core skills: Electronics Engineering and Software Engineering)

Worked as a Research Student to study how FPGA Technology could be applied to a Mechanical Engineering application. The focus of the work moved towards applications in Royal Mail which includes the acoustic monitoring of rolling element bearings in mail sorting machines. The intent was to examine the application of FPGA technology to the task of condition monitoring the rolling element bearings by use of signal processing algorithms to extract key artifacts from the acoustic signals. What was accomplished was a multifunction HDL module that could perform many functions altering its data and control flow path dependent upon the function or sub function that was being executed. This targeted floating-point operation as the there was little work done to date in examining there application to signal processing due in part to logic resource size constraints. More details on this work are contained in the sections that follow.

Knowledge transfer in the form of: Presentations (both at Conference Level and department level), conducting lab tours and the publication of international conference papers.

FPGA Research: Research

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