Sagar Rajendra Kanphade

***** ******* ****** #***, **********, CA 91325

Email: ac1kp1@r.postjobfree.com Contact #: 862-***-**** https://www.linkedin.com/in/sagar-kanphade/ Summary of Specializations:

• Good programming skills - C, C#, VHDL, Python, Verilog for RTL design

• Good Knowledge of coding in ARM assembly, C/C++, Embedded C

• Good understanding of Data structure and Computer Architecture

• Project-based (academic) experience in FPGA prototyping, SoC and RTL design

• Development and interface experience in CAN, I2C, SPI, RS-232 protocols.

• Experience in designing and implementing analog/digital and high-speed circuit design.

• Strong Electrical Engineering fundamentals

• Familiar with FPGA/ASIC Design Flow

• Good understanding of Object-Oriented design concepts, Verification using UVM methodology Education:

Master of Science, Electrical Engineering, California State University, Northridge August 2015 – May 2017 Specialization – Digital and Computer Engineering GPA 3.4 Relevant Courses: FPGA/ASIC Design, System on chip design, VLSI Design Automation and Algorithms, Digital signal processing, Verilog and System Verilog, Advanced switching Theory, Digital System Design Automation and VHDL Modeling, Computer Networking, Network Information security. Bachelor of Engineering, University of Pune, India August 2009 – June 2014 Electronics and Telecommunication Engineering GPA 3.2 Principle Courses Covered: Mobile and Wireless Communication, Digital Communication, Telecommunication and Switching Systems, Television and Video Engineering, Digital Signal Processing, VLSI design, Electromagnetic, Data Structures, Network Analysis, Solid State Devices and Circuits.

Work Experience:

Lab Assistant, California State University Northridge, CA, USA January 2016 – January 2017

• Assisted students in their FPGA/ASIC lab coursework and Projects. Helping them understand the electronic equipment’s such as Digital oscilloscope etc. and simulate electric networks to measure the resultant response. Trainee Engineer, Oasis Technologies Pvt.Ltd, Pune-India June 2012 – November 2014

• Designed PCB Layout, Embedded coding, Troubleshooting, Assembly Programming & Simulation.

• Tested hardware embedded kits with oscilloscope & performed software debugging.

• Microcontroller based system design, sensors and power supply design. Skill Set:

Languages: C#, C++, .Net, VHDL, Assembly Language, Perl, Python, Linux Shell scripting, Embedded C/C++, UVM, System Verilog, Java

Platforms: Linux, Windows

Microcontroller, FPGAs, SoC: Xilinx Vertex 7 series FPGA, LM3S9B96 (ARM Cortex M3 core), STM32F101R8 Microcontroller, ARM11, MIPS and X86

Debugging Tool: GDB, JTAG

MS-Suite: Microsoft Office, Word, Excel, Visual basic, Power point. Tools: Vivado 2015.2(Xilinx), Xilinx SDK, Quartus II Design Software (ALTERA), Microsemi, Keil IDE, MATLAB VCS Synopsys Function Verification, Modelsim, LabView H/W Tools: Digital Oscilloscope, Logic Analyzer, Digital Multi-meters and JTAG debuggers Peripherals & Protocols: UART, SPI, I2C, CAN, ADC, RS-232, Ethernet, TCP/IP Projects:

• Real Time Audio signal processing system.

Study the architecture of the ADAU1761 audio Codec and the Inter-Integrated Circuit (I2C) interface protocol and use it to communicate with an external chip. Study the Inter-IC Sound (I2S) interface protocol and utilize it to exchange audio data with an external chip. Examine the formats in which audio data is stored and processed. Build a simple digital audio processing application with Xilinx Zedboard as a hardware. Test bench in C and VHDL.

• OLED controller IP for Xilinx Virtex-7 FPGA

Designed OLED controller on Virtex-7 FPGA to communicate with the OLED display using SPI interface, implemented and tested on Zedboard. Designed RTL using VHDL. Tool used for - Vivado 2015.2.

• Implementation of Canny Edge Detection using HLS (High-Level Synthesis) Designed an image processing hardware accelerator using high-level synthesis in C++ and designed IP is tested and verified on System on Chip (Zynq 7000-All Programmable SoC, ARM Cortex A9). Simulated and tested this algorithm in MATLAB for verification process. Developed a Python script to parse the image.

• DTMF based device control.

The main aim of this project is to implement an interfacing system to remotely control electrical appliances using DTMF tone. The system can be used in smart homes for home automation as well as in industries to automate process. This was implemented using programming language Embedded C in AVR Studio. Publication:

“Automatic car parking system implemented on a remote-controlled car”

• Publisher: International Journal for Technological Research in Engineering

• Publication Date: 05/09/2014

• URL: http://www.ijtre.com/images/scripts/201-***-****.pdf

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