Manager State University

MEG UEHARA

***********@*******.***

408-***-****

SUMMARY

To obtain a Mask Layout Designer position in the semiconductor industry to apply skills and experience attained and share my interpersonal skills. Excited to work for a dynamic environment with good people.

EDUCATION

SILICON DRAFTING INSTITUE, San Jose, CA

Advanced BiCMOS IC Mask Layout Design Course (Completed July 2017)

CMOS/BiCMOS Circuit Theories:

Fundamentals of transistor, schematic, logic and complex logics

Theories and calculations in layout for Resistance and Capacitance

Sequential circuit, clock delay and clock skew issues

BiCMOS process fundamentals and terminology

Truth tables, Boolean equation & Timing concepts

Device matching and noise reduction in Analog circuits

Antenna issue, latch-up theory & prevention

CMOS/BiCMOS layout techniques:

0.1um 5-layer metal mixed signal BiCMOS technology

CMOS transistor, resistors, capacitors, and diodes

Chip-floor planning techniques

Basic & complex logics, Data Latch D Flip-Flop, Shift Register, SRAM

Guard ring, densities, antennas

DRC and LVS debug

Full custom and top level layout

Placement and routing techniques

Operating systems: Windows, Linux

Layout Tools: Cadence Virtuoso Layout Editor (VLE), Virtuoso XL Layout Editor

Cadence Assura DRC/LVS/Soft-Check, Dracula DRC/Dracula, Chip Assembly Router

Applications: MS Word/Excel

Language: Fluent in Japanese

San Jose State University: B.S. Business Administration, Concentration in Accounting

EXPERIENCE

Canteen Vending, San Jose, CA May 2014 – Feb 2016

District Accounting Manager II

Ecrio Inc., Cupertino, Jose, CA May 2006 – Oct 2013

Senior Accountant

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