Brian D. Gelzinis

*** ******** *****

Melbourne Beach, FL 32951

E-mail : ac1fjs@r.postjobfree.com

Home Phone 321-***-****, Cell (None)

Electrical Engineering Position Desired:

Seeking a position as a Senior Field Programmable Gate Array (FPGA) designer, experienced with both Xilinx and Altera FPGAs and CPLDs.

EDUCATION:

June 1983 Bachelor of Science in Electrical Engineering from the Florida Institute of Technology (BS EE)

August 1989 Master of Science in Electrical Engineering from the Florida Institute of Technology (MS EE in Signal and Information Processing)

EMPLOYMENT:

30 years as an Electrical Engineer (EE-3) for Harris Corporation, Government Communications Systems Division (GCSD), Melbourne, Florida (July 1984 – September 2014).

6 months as an Electrical Engineer for Triple Play Communications, Melbourne, Florida (September 2017 to present date).

EXPERIENCE

July 1984 – September 2014 Electrical Engineer, Level 2-3 Harris Corporation GCSD specializing in Circuit Card Assembly design (first ten years) and Field Programmable Gate Array Design (last twenty years). Please see below for experience specifics.

September 2016 to Present Date – Electrical Engineer, Triple Play Communications specializing in high speed Field Programmable Gate Array Design supporting back end applications to 10 and 12.5 Gbps fiber optic links. Please see below for experience specifics.

FPGA DESIGN EXPERIENCE:

Coded, functionally simulated, lab tested and integrated over fifty FPGA designs of various complexities using the Xilinx Family of FPGAs ranging from XC2000 series devices up to and including Virtex 7 Series FPGA devices along with various Kintex families. Coded, functionally simulated, lab tested and integrated a dozen FPGA designs using Altera Stratix V family of FPGAs. FPGA design functionalities have included:

Microprocessor Interfaces

Development and design of interfaces between other FPGAs in collaboration with other FPGA designers

High speed interfaces including PCIE Express, 1 Gb Ethernet, DDRii SDRAM, QDP2+ SRAM

Design and integration of various Xilinx and Altera IP cores including PCIE, DPRAM, RAM, FIFOs, Ethernet, LDPC Encoder/Decoder, Turbo Encoder/Decoder

Signal and Baseband Data Processing functions such as Block and Hybrid Interleaving/Deinterleaving, Viterbi encoding/decoding, FFT Processing, FSK modulation/demodulation, QPSK modulation/demodulation, Data Storage Interfaces.

Designs with clock/data rates up to 500 MHz

Control and Status Interfaces to various ADCs and DACs

Designed FPGA interfaces to SPI and I2C devices

JTAG interfaces for FPGA Configuration and FPGA Test

Experienced with the design and use of Chipscope (Xilinx) and Signal Tap (Altera) Cores for FPGA lab testing

Authored and owned the following types of FPGA Design Documents:

oFPGA Design Specifications

oPeer, Preliminary Design Review (PDR), Critical Design Review (CDR) Packages

oInterface Control Documents (ICD)

oVersion Description Documents (VDD)

oTest and Functional Verification Procedures

Served as Lab Custodian on various programs

Oversaw and managed the testing of FPGA designs being performed by junior engineers.

Experienced in the complete FPGA design cycle, from defining requirements to architecting the overall design to unit integration and test

Currently involved in high speed FPGA design using Kintex Ultrascale FPGA GTH Transceivers supporting line rates up to 100 Gbps on fiber optic links through QSFP modules. Also performed schematic capture of the circuit card assembly that will host the target FPGA device.

FPGA-RELATED DESIGN LANGUAGE EXPERIENCE:

VHDL

Verilog

C++

FPGA DESIGN AND DEVELOPMENT TOOL EXPERIENCE:

Fluent in the use of the following FPGA Firmware/Software Design and Development Tools:

Xilinx ISE Design Suite

Xilinx Vivado Design Suite – functional simulation, design synthesis, Implementation and Bitstream generation

Xilinx Core Generator System (Coregen)

Xilinx Chipscope

Quartus II Design Software

Quartus II MegaWizard Core Generator

Quartus Signal Tap

Cadence Simvision Functional Simulation Tool

Visual Elite

Mentor Graphics xDX Designer (PADVX.0) – schematic capture, symbol editor, netlister

MANAGEMENT EXPERIENCE:

Lab custodian and managed the labs on several different programs while with Harris Corp.

Mentored and tutored junior engineers on the use of FPGA development tools and FPGA design.

Led teams on cost and schedule for FPGA design and development on several proposals while with Harris Corp.

TEST EQUIPMENT EXPERIENCE:

Logic Analyzers

Oscilloscopes, including Storage Scopes

Spectrum Analyzers

Function Generators

Power Supplies

Frequency Generators

Counter/Timers (HP)

Multimeters

COMPUTER OPERATING SYSTEM EXPERIENCE:

Windows Versions 97, 8.0, 10.0, NT, Vista, DOS

UNIX

DOCUMENTATION TOOL EXPERIENCE:

Fluent in the use of the following design documentation tools:

Microsoft Office (Word, Excel, etc)

PowerPoint

Visio

Doors

ClearCase

CLEARANCES:

Have held and voluntarily relinquished in good standing the following clearances:

DOD Secret (Debriefed in September, 2014)

X Clearance (Debriefed in July of 1996)

REFERENCES:

Keith Riffee: Engineering Manager at Triple Play Communications, TPC 250 East Dr F Melbourne FL 32904

oE-mail: ac1fjs@r.postjobfree.com

David Slapo: Engineering Coworker at Triple Play Communications, TPC 250 East Dr F Melbourne FL 32904

oE-mail: ac1fjs@r.postjobfree.com

Catherine De Meyer: Engineering Coworker at Harris Corporation, Palm Bay, Florida

oPhone: 321-***-****

oE-mail: mailto:ac1fjs@r.postjobfree.com

Raymond Defillips: Engineering Coworker at Harris Corporation, Palm Bay, Florida

oE-mail: ac1fjs@r.postjobfree.com

David Larson: Coworker at Harris Corporation and currently design collaborator with TPC at Cisco Systems, 7025 Kitt Creek Rd, Research Triangle Park, NC Bld 8

oPhone: 919-***-****

oE-mail: ac1fjs@r.postjobfree.com

OTHER DESIGN EXPERIENCE:

Prior to becoming a full-time FPGA designer, spent ten years as a circuit card designer with the following responsibilities:

Circuit Card Assembly (CCA) Schematic Capture

Preliminary CCA component placement

Interfacing with CCA Layout, Fabrication and Assembly

Card Test

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