Sr. ASIC Digital Design Engineer

Thomas Marshall

E: *****@********.*** M: 503-***-**** Williamsport, PA 17701

Dear HR Manager:

I would be an invaluable asset to your company based on my character, work ethic, job experience, and education. I have a BS in Electronics Engineering (3.8 GPA) and an AAS in Electronics Technology (4.0 GPA) with more than 18 years in digital ASIC design experience.

I am an expert in managing risk and at finding and solving problems before they become bigger and detrimental to the product and company.

My most recent employer, Synopsys, Inc, through a round of cost reductions, has relocated its SATA design features and support efforts to China, and as such my position as Sr. ASIC Design Engineer has ended. Given the majority of its digital designs are located outside the United States, it is time to move on to bigger and better things after 16.5 years of loyalty and dedication.

During my time at Synopsys, I have primarily worked on Serial ATA Host and Device controller architecture and design, from pre-specifications as a contributing member of the SATA Org consortium through endless features and enhancements. The SATA design was highly configurable supporting dozens of configurations that could interface to customer SOC designs and contained as many as 28 asynchronous clock domains.

I have also designed on FPGAs and have worked on Graphics, T1/E1, UART, AMBA (AHB, AXI, Ace-Lite), PCIe, and been responsible for documentation, CDC and validation (VCS/DVE, UVM, VMM, SVAs), Spyglass and lint tools, DC synthesis, PrimeTimePX, as well as training and mentoring new designers and the design team in China. Finally, I have also participated in direct customer support via customer conference calls on a regular basis, with consistent positive feedback.

In my spare time over the last 14 years, I have also been continually working on artificial intelligent data analysis algorithms primarily in Perl and have been wanting to combine my experience in both ASIC and financial market worlds for a long time; I have millions of ideas that would translate to the bottom line. I am currently working on my own system/algorithm design on a Xilinx KCU105 development board with a Kintex UltraScale XCKU040 FPGA, using the Vivado Design Suite.

I am also the most dedicated, committed, honest, and direct person you will meet.

I can provide many professional references to attest to my character and experience. I would be very excited to discuss Design Engineering positions with you.

I appreciate any consideration given me.

Sincerely,

Thomas Marshall

Thomas Marshall

E: *****@********.*** M: 503-***-**** Williamsport, PA 17701

ASIC Design

I am a meticulous problem-preventing/problem-solving Sr. ASIC Design Engineer who goes above and beyond to meet deadlines and produce top-quality ASIC designs. I am extremely dedicated, committed, honest, innovative and enthusiastic. I prefer an East Coast location or a work-from-home arrangement but am open to all possibilities.

Professional Experience

AI Data Solutions, LLC, Davenport, FL - 2017 – Present

Self Employed:

FPGA/ASIC Design contract work

Market data analysis (machine learning, etc.)

Currently working on FPGA based proprietary machine learning trading system design

Synopsys, Inc, Hillsboro, OR - 2001 – 2017

Sr. ASIC Design Engineer:

Micro-architecture, Design and Verification of highly configurable, multi-clock domain Serial ATA Host and Device controllers, with many enhancements and features, including:

Device Sleep

AMBA AHB/AXI, Ace-Lite

Memory, Data and Address protection and error correction (DesignWare Foundation component) integration

Performance improvements, as well as many PHY interface enhancements

Contributing member of SATA Org consortium

Mentored new designer and junior engineers

Worked on PCIe and AMBA design and validation, as well as formal verification, coverage and other methodology improvement projects.

Micron Technology, Rendition Division, Hillsboro, OR - 1999 – 2000

ASIC Design Engineer: Micro-architecture, Design and Verification of Computer Graphics RTL blocks.

Cadence Verilog design and simulation

Virsim Debugging

Synopsys Design Compiler synthesis and static timing analysis.

Completed an RTL block involving control register access, memory requests and arbitration, critical circuit timing control and FIFO interaction.

Designed and tested a complex, re-readable hardware FIFO.

Designed and tested hardware Linear Interpolator by hand.

Wrote tests in C and Verilog to test Hardware C Models. Wrote other hardware models in C.

ADC Telecommunications, Kentrox Division, Beaverton, OR - 1991 – 1999

Sr. Technician: Design of an Altera FPGA for testing digital T1 circuits in Test Engineering. Prior to that, responsibilities included:

Installation, maintenance, upgrade, repair and modification of complex computer controlled equipment

Training of other personnel.

Maintained the budget for, and a supply of, equipment spare parts, hardware and software.

Manufacturing Engineering backup and projects including C++ programs to optimize machine set-ups in the surface mount area.

Education

BS Electronics Engineering GPA: 3.8 (Magna cum Laude)

Oregon Institute of Technology, Beaverton, OR

AAS Electronics Technology GPA: 4.0

Pennsylvania College of Technology, Williamsport, PA

Honors

Dean’s List

John A Savoy Scholarship

Certificate of Recognition as a Student Tutor

Trustees Award (Commencement)

Technical Skills

Recent Experience

Proficient in all tools and phases of ASIC digital design and validation

Xilinx Vivado Design Suite

Xilinx Kintex UltraScale FPGA KCU105 development kit

System and micro-architecture, design and validation

Serial ATA Host and Device controllers and features

Data-bus Interfacing design (AMBA – AXI, AHB, Ace-Lite)

Complex data conversions, data protection, error correction

Large number asynchronous clock domains, CDC

Project owner of multi-clock domain CDC planning, design and validation

Verilog

VCS

VMM, UVM, SVAs for feature and code coverage

Virsim and DVE Waveform Analyzers

Synopsys Design Compiler

Synopsys Prime Time including PX

Synopsis FPGA Express and Synplicity

Spyglass and Leda (CDC and lint)

Synopsys coreConsultant

Perl, Tcl, Csh, Make

C/C++

Synopsys DesignWare Foundation component integration

Some Pcie knowledge

MS Office, Adobe documentation tools

Prior Experience

Virsim Waveform Analyzer

VHDL

Altera Max Plus II FPGA design tools and hardware

Mentor Graphics design tools(ModelSim, Leonardo)

Hardware FIFO Design

High-speed data communications equipment (T1/E1)

ORCAD schematic design tools

PSPICE (Design Lab)

knowledge and use of:

Multi-meters

Oscilloscopes

Function Generators

Spectrum Analyzers

Logic Analyzer

Assembly language

Configuration and debugging of DOS, Unix and Windows

Configuration, debugging and repair of computer hardware

Communications setup and protocols

I also completed several design projects in my studies at Oregon Institute of Technology, in the areas of Digital, Analog, Microprocessor, Assembly and C++. These projects were of moderate complexity. I also very successfully completed a Sr. Project, consisting of a T1/E1 Error Generator FPGA, for testing error detection in real Data Telecommunications products. This project was of much higher complexity and functioned according to the project plan.

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