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Engineering Design

Location:
Chennai, TN, India
Posted:
July 18, 2017

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Resume:

Srikanth Sanikommu

D.no : *-**, Email: ac1cvi@r.postjobfree.com

Thuvvapadu, Contact:975*******/957-***-****

Konakanamitla(mandal),

Prakasam district, A.P.

Career Objective:

I would like to be a part of a reputed corporate where i can constructively build my career working along with dedicated and committed team that is helpful to improve my potentiality. Education profile:

Course School/College Board/University

Year of

passing

Percentage

& CGPA

M.Tech

VLSI DESIGN

VIT University,

Vellore

VIT University

2018

8.0

B.Tech(ECE)

M.V.R College of

Engineering and

Technology,Vijayawa

da

J.N.T.U

Kakinada

2015 7.18

Intermediate

Narayana junior

college,Vijayawada

Board of Intermediate

Education, AP

2011 86.7

S.S.C

Z.P. High

School,Konakanamitla

Board of Secondary

Education, AP

2009 73.6

Technical Skill Set:

TOOLS:

Cadence Virtuoso ADE

Synopsys

Mentor graphics.

Languages:

Verilog HDL

PERL

System verilog

Area of intrest:

ASIC Design

Digital Design

Projects:

A Brief study and analysis of Power dissipation and DQ delay of Energy recovery Flip-Flops

ASIC implementation of 8-Point Integer 1-D DCT/IDCT for the HEVC standard

Dual LFSR Reseeding for Low power Testing

FPGA implementation of Heart Rate Monitoring System

Design of FINFET using TCAD

Co-Curricular Activities:

Presented paper on “8-Point Integer 1-D DCT/IDCT for the HEVC standard” in the 5th International Conference on Contemporary Engineering held at Madha Engineering College, Chennai on March 25, 2017.

Presented paper on “A Brief study and analysis of Power dissipation and DQ delay of Energy recovery Flip-Flops” in the 13th International Conference on Science Engineering and Technology (SET) held at VIT, Vellore on November 10, 2016.

Presented paper on “FPGA implementation of Heart Rate Monitoring System” in the 14th International Conference on Science Engineering and Technology (SET) held at VIT, Vellore on May 3, 2017.

Participated in workshop on “Industry-Academia Conclave 2017” in VIT University.

Participated in workshop on “Two Days National Level Hands On Training Program On TCAD for IC Design” in VIT University.

Participated in workshops on “IEEE colloquium on emerging trends in electronic systems”, “SKILL Programming”.

Achievements:

won first prize Kabaddi in central zone which was held in under JNTU Kakinada university

won first prize Kabaddi in C zone (2 times) which held in under JNTU Kakinada university

Personal Information:

Name - S.Srikanth

Father s Name - S.Venkateswarlu

Date of Birth - 16/06/1994

Language Known - Telugu, English

Marital Status - Single

Nationality/Religion - Indian / Hindu

Declaration:

I hereby declare that the above furnished details are correct and true to the best of my knowledge and belief.

Place:

Date: Srikanth .S



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