Jr. Verification Engineer
Resume:
SRIKANTA S M
*****************@*****.***
Objective Dynamic and career oriented engineering professional with hands on experience in designing VLSI/Embedded integrated circuits. Looking for a responsible position with a view to utilize and enhance my skills and experience towards professional growth.
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Skills Domain Knowledge
Experience in writing RTL models in Verilog HDL and Test-benches in System Verilog.
Experience in using industry standard EDA tools for the front-end design and verification.
Knowledge in APB,SPI,I2C Communication Protocols
Verification Methodologies
Coverage Driven Verification using SV, UVM.
Experience Jr. Verification Engineer July 2015-Present.
Invendis Technologies.
Responsibilities:
Involved in isolating and identifying design bugs.
Implemented test plans to verify unit, subsystem, and chip level functionality in a complex SOC environment.
Working experience with interfaces like SPI and I2C Peripherals.
Created constrained random based test-bench and test cases, to ensure adequate feature and code coverage.
Performed VIP Environment development.
Generating Random based stimulus for test cases.
Design Verification Trainee Sep 2014 – Feb 2015.
Maven Silicon
Responsibilities:
Implemented the Dual Port Ram using Verilog HDL independently.
Architected the class based verification environment using system Verilog.
Verified the RTL model using class based UVM TB.
Generated functional and code coverage for the RTL.
Projects
I2C Bus Interface Verification Invendis Technologies
Description: I2C interface works as Serial Communication Protocol.
All other IC’s hooked with two pins (SDA, SCL) .
Roles:
Architected the class based verification environment using System Verilog.
Generating the Test cases to verify the functionality.
Features Verified:
Unidirectional and Bidirectional data transfer.
Acknowledgement response to convey Successful Transfer.
Repeated START test case.
Clock Stretching test case.
SPI IP Core Verification Invendis Technologies
Description: This core can operate in 8 bit or 32 bit bus data mode.
The 32 bit mode is fully WISHBONE compatible.
Roles:
Generic sequence to configure master and slave.
Developed Coverage Model and Scoreboard for IP.
Features Verified:
Full duplex synchronous serial data transfer.
Variable length of transfer word up to 128bits.
Rx and Tx on both rising or falling edge of
Serial clock independently.
Qualification
Certified Advanced VLSI Design and Verification course
From Maven Silicon VLSI Design and Training Centre, Bangalore
Year: February 2015
Bachelor of Engineering (July-2014)
From A P S College of Engineering affiliated to VTU
Discipline: Electronics and Communication Engineering.
Declaration
I hereby declare that the information given here with is correct to best of my knowledge.
Place: Bangalore Date: June 2017
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