Engineer Design

KARTHI S

Bengaluru, Karnataka ****** (C) +919********* ***********@*******.***

Professional Summary

Functional Verification engineer and Team Lead with over 13+ years of experience in verification of ASIC/FPGA at unit as well as chip level, architecting complex verification environment from scratch and creating verification plan, test plan - architecting to

verification closure.

Skills

Team Leader and Technical Leadership System Level integration and testing

Chip-level/unit-level/SOC verification techniques Strong problem-solving

Programming Languages: C, C++, Perl, Shell Scripting Communication skills and art of presentation

Verification Methodology: Fusion An extrovert person always ready to take initiative.

Protocols: PCIe, Ethernet, Infiniband, ASIC Interconnect Aim to achieve excellence in every assignment

Bus, High Speed Serial 6G/4G link Quick Lerner and have multiple experience of

HDV/HVL : VHDL successfully pulling off projects in trouble.

EDA Tools : Mesa, CteMantis, Modelsim, NC Sim Agile Methodology

Architecting verification environment and reusable verification methodology

Work History

Verification Engineer 03/2015 to Current

IBM India Pvt. Ltd

Team Leader for Z System Core RAS Verification team of 6 members.

Technical Leadership of Ethernet Data Router SOC Verification.

Developing complete verification environment plan and implementing them.

Developing testbench from scratch, closely involved in defining verification/test/coverage plan and regression management.

Guiding and mentoring the team members, delegating work and constantly working on improving the methods that helps meeting aggressive deadlines keeping in check quality and predictability.

Providing all support needed for the progression of the project in the right direction.

Z System Core RAS Verification (Ongoing Project): IBM System z processor cores are designed with a high focus on Reliability, Availability and Serviceability (RAS). The hardware is designed to support a high tolerance against errors and the ability to recover from it and maintaining a valid architectural state. The team received Execution excellence award for this project.

Ethernet Data Router SOC Verification: This is a System-on-Chip (SOC) ASIC meant for system -Z applications. This chip supports both storage and networking applications. The storage protocols include FICON and FCP whereas OSA (Open System Adaptor) is the networking protocol used. The achievement here is that this chip went to production in the first pass itself and I have also received Execution excellence award.

Staff R & D Engineer 02/2012 to 02/2015

IBM India Pvt. Ltd

Completely responsible for GPIO, DCR, I2C and UART Verification.

Responsible for unit verification of Link interface, whose functionality is protocol conversion between Infiniband packets and the internal Interfaces.

Involved writing the different drivers/generators/checkers to validate the conversions and protocol validation.

Mentoring team members and new comers to help them adapt to IBM Verification methodology and Project details.

ICBP (PCIE interface) unit level verification: ICBP (Intersystem Cluster Bus over PCIe), the next generation of System z Parallel Sysplex Coupling Facility Links for short distances (up to about 150 meters) with low latency and high bandwidth. This will be packaged in the Z- processor chip as part of the PCI Bridge Unit.

Crocodile: CROC - Converged RAID on Chip, used on a Direct Attached Storage (DAS) RAID Controllers that connect to Solid State Drives (SSD) or Hard Disk Drives (HDD - spinning drives).

R & D Engineer (A and B) 01/2006 to 01/2012

IBM India Pvt. Ltd

Responsible for unit verification of Link interface, whose functionality is protocol conversion between InfiniBand packets and the internal Interfaces.

Writing the different checkers to validate the conversions and protocol validation.

Verification of High Speed Serial 6G/4G Link verification which included POR sequence, PLL looks and Link training.

Cayman: Cayman is a coupling adapter for Parallel Sysplexes built with System z servers. The Cayman adapter allows to transfer messages with low latency via an InfiniBand link/physical layer.

Hurricane: Hurricane is an integrated L4 cache, memory controller and scalable building block controller for the Potomac/Nocona processor. It provides scalability for up to four processors per node and up to eight nodes.

Design Engineer 01/2004 to 12/2005

RASS IT SOLUTIONS Pvt Ltd

Designed and implemented (VHDL) keypad encoder for Contact-less smart card reader in a Spartan2E family (XC2S100E) Xilinx FPGA.

Actively took part in testing and integration of the complete system.

Contactless Smart Card Reader: Single-package type Contactless Smart Card Reader combining controller, electronics and antenna. The reader shall be capable of reading data from any 15693 or 14443 A and B contactless smart card or equivalent, and transmitting that data in SIA standard Wiegand format, Serial Format using RS232/485, USB 2.0 format and Ethernet type.

Engineer 10/2003 to 10/2004

Ananth Technologies Ltd

Designed and implemented glue logic and self-learning feedback logic on CYPRESS CPLD (CY37512VP208) for Thyristor Rectifier Control System.

Actively took part in testing and integration.

Thyristor Rectifier Control System: Digital control system for regulating the DC output Voltage and DC output Current by using feedback inputs from the Isolating Voltage and Current Sensor.

Education

Diploma: Electronics and communication Ghousia polytechnic - Bangalore

1997

Bachelor of Engineering: Electronics and communication

2001

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