Customer Analysis

CHARLES P. TODD

**** ***** ***** *****, ********** Tx 75007

(214) 497- 8685

********@*****.***

OBJECTIVE:

My desire is to secure a position where my electronic skills and background employment will be beneficial to the company. My training with hardware and software will indicate to you that I am prepared to make valuable contributions to your organization.

EDUCATION / KNOWLEDGE BASE:

NATIONAL EDUCATION CENTER, Bryman Campus, Houston, Texas

Associates of Applied Science in Electronic Engineering Technology: GPA 3.2/4.0

FAILURE ANALYSIS RELATED HARDWARE/TECHNIQUES:

Emission Microscopy (EMMI) Schematic/Layout Analytical Micro-sectioning

Liquid Crystal Analysis FIB Microscopy (Single & Dual Beam)

Scanning Electron Microscopy X-ray Analysis Oscilloscope Skills

Laser Isolation Plasma Etching

Optical Microscopy Energy Dispersive X-ray Analysis Image Processing

Internal Mechanical Probing Calibration Techniques Soldering Techniques

Automated and Manual Curve Tracing Sample Preparation Techniques Fail-site Isolation Techniques (QFI)

Scanning Acoustic Microscopy (OKOS/Sonix)

RELATED SOFTWARE AND COMPUTER SKILLS:

Microsoft Office Suite Knight Database Adobe Photoshop

Semicaps Image Capture Sys. Cadence Database UNIX/X Windows (SUN Workstation)

WORK EXPERIENCE:

FAILURE ANALYSIS SENOIR TECHNICIAN - PRIORITY LABS, Dallas, Texas June 2016 - Present

Responsible for timely analysis of internal and external customer returns of various HVAL, ASP, ASIC, WTBU and Other devices.

FIB Analysis - Responsible for timely analysis with the FEI 200 dual beam doing cross-sectioning and design edits.

Implemented 1 new analysis technique.

Responsible for Cross-section Analysis on various devices.

FAILURE ANALYSIS SENOIR TECHNICIAN - EVANS ANALYTICAL GROUP, Irvine, California October 2010 - June 2016

*An ISO 9001:2000 certified startup independent lab.

Performed Electrical and Physical failure analysis on customer returns of various CHIP SCALE, QFP, FLIP-CHIP, BGA and Other devices.

Responsible for timely analysis of external customer returns of various CHIP SCALE, QFP, FLIP-CHIP, BGA and Other devices.

Analysis required the use of electrical bench testing, global fail-site isolation techniques, wet chemical, deprocessing, parallel lapping as well as plasma processing. Analysis was performed at both Die Level and Packaged Level.

Implemented 1 new analysis techniques. The implementation maintained customer quality and satisfaction as used on Chip Scale Devices

Customer interfacing with various customers to receive feedback on the analysis.

ELECTRONIC SYSTEMS TECHINAL LEAD INSTRUCTOR - ATI, Dallas, Texas May 2009 - October 2010

Instruct students on various electronic systems (Fire Alarm, Intrusion Detection, and Audio System Installation and Integration) - Semiconductors and Integrated Circuits, Job-Site Safety, Digital components, Basic Fiber Optic Techniques, Voltage Measurements, Basic Test Equipment, Ohm's Law and ETC.

Responsible for timely internal feedback on students' progress.

FAILURE ANALYSIS SENOIR TECHNICIAN - PRIORITY LABS, Dallas, Texas December 2005 - January 2009

Quality Steering Teams (QST) - Worked with 3 QST to insure techniques were in place to guarantee cycle time, quality and customer satisfaction. Work resulted in a 90% on time delivery of analysis with a 4 out of 5 customer satisfaction rating.

Responsible for timely analysis of internal and external customer returns of various HVAL, HPA, ASIC, WTBU and Other devices. I successfully resolved 94% of my analysis jobs.

FIB Analysis - Responsible for timely analysis with the FEI 600 single beam doing cross-sectioning and design edits.

Implemented 5 new analysis techniques per year on average. The implementation maintained customer quality and satisfaction as represented in the QST results.

Quality Team (QT) - Coordinated the work load of 8 analysts to meet customer requirements. The results are represented in the QST discussed above.

Customer Liaison interfacing with 4 customers to receive feedback on the analysis priorities and analysis quality. The results are as described in the QST.

Maintained 5 pieces of equipment including 2 SEM's, 2 automated jet etch systems and a probe station. The up time for the SEM's was greater then 80% and the remainder of the equipment was available for analytical use 100% of the time.

FAILURE ANALYSIS TECHNICIAN - TEXAS INSTRUMENTS, Stafford, Texas May 1989 - December 2005

Performed Electrical and Physical failure analysis on customer returns of various CMOS Microcontroller / microprocessor, SPARC, DSP and EPROM / Flash devices. Customer expectations were meet with a better than 80% average success rate across all product types. Analysis required the use of electrical bench testing, global fail-site isolation techniques, wet chemical, deprocessing, parallel lapping as well as plasma processing. Analysis was performed at both Wafer Level and Packaged Level.

Quality Team - As a QT member, new approaches to reduce cycle time and improve failure resolution were developed. Due to the development of new techniques Houston Device Analysis Operation HDAO remained over 50% success rate across all devices and was 80% on time. One particularly impressive analysis in the SPARC Group took 600 units to determine the root cause of the problem. In performing this analysis 3 new techniques were developed to meet the specific requirements of the device being deprocessed.

FIB Analysis - Responsible for timely analysis with the FEI 235 dual beam doing cross-sectioning, solder bump clean-up, design edits and circuit repair. I also have basic knowledge on Micron 900 series for backside edits.

Weekly and daily interfacing with customers was required to coordinate the work load as well as understand the fail-modes of the devices being analyzed; because of the meetings we maintained high customer satisfaction.

Optimized wet chemicals and plasma etching techniques which made possible constant improvement of the overall analysis process. Some of these improvements were significant interest to the general failure analysis community to be published at the International Symposium for Test and Failure Analysis.

REFERENCES AVAILABLE UPON REQUEST

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