Summary

Highlights

Accomplishments

Experience

William Stanton

*** ****-**** **** ****, Rush NY 14543

Home: 585-***-**** Cell: 585-***-****

ac152y@r.postjobfree.com

Experienced Electrical Engineer and former United States Air Force Captain experienced in digital electronic design, design for testability and hardware security. Over 8 years of experience in FPGA digital design (for terrestrial and space-borne applications), verification, and laboratory validation testing. United States Government Secret Clearance

(SSBI, Inactive)

Enthusiastic and experienced engineering leader

with 8 years of fast-paced operational leadership

and research experience

Experienced in Military/Government

acquisitions processes

Systems Planning, Research, Development and

Engineering - Science and Technology Manager

Level I and II certified from Defense Acquisition

University

8+ years experience using VHDL, C/C++,

MATLAB, Python, and multiple assemblers

Software development for Micro/Picoblaze, PIC

8/16/32-bit, ARM7/9, MSP430, ATmega

Inducted into the IEEE Electrical and Computer Engineering honor society Eta Kappa Nu (HKN) for being within the top 10% of all electrical and computer engineers while at the Air Force Institute of Technology. Company Grade Officer of the Quarter: High Performance Computing Division, Air Force Research Laboratory, Rome, NY - 2nd Quarter 2012, 2nd Quarter 2013 and 1st Quarter 2014 for outstanding military leadership, mentorship, and community involvement. Major Military Decorations: Army Commendation Medal, Air Force Achievement Medal, Meritorious Unit Award, Afghanistan Campaign Medal (2 Service Stars) Harris Corporation - Space and Intelligence Systems March 2015 to Current Electrical Engineer III

Rochester, NY

- Led internal research and development effort to integrate new sensor input chain into mirror steering assembly controller

- Module-level FPGA lead and designer responsible for designing robust control systems for space-borne imaging systems

- Assisted in the verification efforts of three major FPGA designs in latest imaging satellite design; participated in board, module, and sub-system-level design validation testing Air Force Research Laboratory (AFRL) - Information Directorate June 2013 to December 2014 Deputy Branch Chief, Integration and Transition Branch Rome, NY

- Assisted with branch leadership, mentored/supervised junior officers in multi-disciplinary engineering and secure computing

- Oversaw technical evaluation and review of branch engineers' performance in meeting research objectives

- Key player in helping Information Directorate meet Air Force research objectives for cyber-security Education

Air Force Research Laboratory (AFRL) - Information Directorate March 2011 to December 2014 Computer Architecture Design Engineer

Rome, NY

- Researched and developed solutions for a multi-level secure cache within multi-core processors

- Led innovative FPGA prototyping and design verification for AFRL's $3M Secure Processor & Trusted Router programs

- Liaised with Department of Defense, academic and industry leaders to accelerate secure processor design and research

Air Force Institute of Technology 2011

Master of Science: Electrical Engineering

Wright-Patterson AFB, OH

Thesis title: Circuit DNA Extraction and Digital Key Generation Method Using Field Programmable Gate Arrays

Rochester Institute of Technology 2009

Bachelor of Science: Electrical Engineering

Rochester, NY

Minor in Aerospace and Leadership Studies