Design Engineering

Curriculum vitae

Name:- KAVYA B.S

Email ID:- ac14ez@r.postjobfree.com

Mobile number:- 998-***-****

Carrier Objective

Looking for an organization that will help me to develop my technical skills Educational Qualification

Name of the Institute

Course

Board/

University

% of marks

AUDEN HIGH SCHOOL

Bangalore

S.S.L.C

Karnataka

Secondary Education

Examination

Board

65.76%

P.E.S PU COLLEGE

Bangalore

Pre-university

Karnataka Pre-

University Board

57.66%

PCM

(65.33%)

B N M I T

Bangalore

B.E [ Electronics and

communication]

[Y.O.P-2011]

Visvesvaraya

Technological

university

54.04%

SAPTHAGIRI COLLEGE OF

ENGINEERING

Bangalore

M.Tech [VLSI Design

and embedded systems]

[Y.O.P-2015]

Visvesvaraya

Technological

university

68 %

Project Profile

Project : “Design and Implementation of an Efficient Majority Logic Fault Detector/Decoder” Description:

Memory in digital circuit is used for storing as well as retrieving data that are needed at particular time. Encoding and decoding are the two basic operations that are responsible for writing into memory and reading from memory. As a result of technology scaling and higher integration densities there may be variations in parameters and noise levels which will lead to larger error rates at various levels of the computations.

Error correction codes are commonly used to protect memories from so-called soft errors, which change the logical value of memory cells without damaging the circuit. As technology scales, memory devices become larger and more powerful error correction codes are needed. The proposed work focuses on the design of an efficient Majority Logic Detector/Decoder

(MLDD) for fault detection along with correction of fault for memory applications Self-judgement

Passed in RED CROSS examination conducted by THE KARNATAKA STATE RED CROSS BRANCH

Completed junior level program in ALL INDIA GENERAL KNOWLEDGE EXAMINATION

Participated in Educational testing centre(ETC) conducted by THE UNIVERSITY OF NEW SOUTH WALES

Paper entitled “Survey on Error Detection and Correction Schemes for Memory Applications” is published by International Journal of Scientific and Engineering Research (IJSER)

Certificate of Paper Publication by IJSER

Technical Skills

Hardware languages:

VHDL

Verilog

EDA tools:

Cadence

Mentor Graphics

Competencies

Willingness to learn.

Highly motivated to work as a team.

Strongly believe in hard work, experience and being practical. Area of interested field

Back End Design

Physical Design

Personal Profile

Name:- KAVYA B.S

D.O.B:- 12/05/1986

Fathers name:- SHIVEGOWDA B.C

Mothers name:- GOWRI K.G

Permanent address:- #1437/1, janani, 11th main, 2nd stage, west of chord road, Mahalakshmipuram, Bangalore-560086

Phone:- 998-***-****

Nationality:- Indian

Language known:- Kannada and English .

Declaration

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars. KAVYA B.S

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