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Electrical Engineering Design

Dallas, Texas, United States
August 31, 2017

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Zhangjie(Nate) Pan

Dallas, TX 972-***-****


Objective statement

Master of Electrical Engineering graduate with 4-year semiconductor industry experience is interested in Electrical Engineering related position. Experience including VLSI design, power management IC design and data converter modeling and verification. PCB board design.


Master of Electrical Engineering University of Texas at Dallas GPA:3.3 2014 -2016

Bachelor of Mechanical Engineering Guilin University of Electronic Technology GPA:3.3 2005 - 2009

Academic Projects

PCB Programming and Testing Divercety, LLC Intern Jul. 2017

Printed Circuit Board programming and failed board trouble shooting.

Optimizing PCB Assembling working flow, improving productivity.

ADC Mixed Signal Circuit Design and Verification System Level Design Lab RA Aug. 2016

Designed Analog-Digital Converter(ADC) mixed signal circuit with RTL level and transistor level design.

Modeled circuit with Verilog and Verilog A/AMS. Wrote test bench on Spectre and Cadence AMS Designer.

Buck Converter Circuit Modeling and Validation with MATLAB Simulink Nov. 2016 - Dec. 2016

Read and reviewed academic papers on buck converter design with PID feedback control.

Analyzed feedback design with MATLAB. Simulated the whole circuit with MATLAB Simulink with physical model.

Power Electronics Lab Buck Converter Investigation Aug. 2016 - Dec. 2016

Investigated steady state and transient performance of buck converter with TI Buck TPS 54160 board.

Used laboratory tools such as power supply, multi-meter, oscilloscope and load to implement experiments.

Folded Cascode Amplifier Design Jul. 2015

Constructed an amplifier with Avd 85dB, CMRR 80dB, PM 60, GBW 10MHz, SR 12 V/µs, OVSR 1.4V.

Enabled schematic design and simulation with Cadence Virtuoso. All required specs were meet.

16-bits Multiplier with IBM 130nm Technology Design Aug. 2014

Implemented and synthesized RTL design with Verilog HDL in Model Sim IDE and Synopsys Design Vision.

Devised Standard cell library layout and schematic with Cadence ADE/Virtuoso.

Optimized chip area with EDP considered. Library characterization was done by Liberty NCX.

Placed and routed final layout with Cadence Encounter. Prime time was used for static timing analysis.

Thickness Measuring System of Film Laminator Design Aug, 2008 to Jun, 2009

Design a film thickness-measuring sensor based on resistance strain gauge to detect the thickness.

Design a constant current source circuit and an amplifying circuit for the sensor to magnify the signal.

Complement PCB layout with Altium Designer.

Micro-scale Atomic Force Microscope May, 2015

Design a 2-D actuator that is able to scan 10um*10um area and a sensing cantilever is able to detect 1nm deflection. Oxidation, Lithography, DRIE Etching are used in the processing. Three masks are designed with Solid Work.

Relevant courses

Analog IC Design Advanced Analog Circuit Design VLSI Design Advanced Digital Logic

Power Management Power Electronics Active Semiconductor RF IC Design

Work Experience

Research Institute of China Electronics Technology Group Corporation Jul. 2009 - Apr. 2013 Silicon Carbide Process Technology Development R&D Engineer

The project team focused on the R&D of the growth and processing of silicon carbide substrate. I was mainly responsible for the development of Polishing /CMP process.

Successfully developed low surface roughness CMP Technology. The average roughness (Ra) of the SiC wafer was enhanced from 1nm to below 0.3nm (the best one achieved 0.073nm).

Successfully developed the small-scale production process. The wafer processing efficiency was enhanced from less than 10pcs/day to 144pcs/day (2 84pcs/day (3

Successfully developed CMP process with differentiations. Optimize process parameter individually for Silicon face and Carbon face for best quality and lowest cost.

Successfully developed the process monitoring technique. This achievement realized the comprehensive monitoring approach by using bright lights, differential interference microscopy (DIC), scanning electron microscopy (SEM), atomic force microscopy (AFM) and other detection tools jointly.

Prepared process manual for all developed processes. Provided trainings to the other team members to make sure they could capture the essential skills and implement the process independently.

Corporate Training

Statistical Process Control (SPC) training. Knowing DOE method and problem shooting method based on statistics.


Zhang-jie Pan, Bin Feng, Lei Wang, Jian-min Hao, “Comparative Chemical Mechanical Polishing Studies of SiC 0001 and SiC 000-1 Surface”, Equipment for Electronic Products Manufacturing, vol. 42, no. 4, pp. 19-23, Apr. 2013.

Awards and Certifications

Winner of "Academic Excellence Award" for 4 consecutive years Oct. 2006 - May.2009

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