Hardware, PCB, electronics

Steve Ding

C: 613-***-**** ***.****@****.**

PROFESSIONAL SUMMARY

Background in electrical & computer engineering; years of experience in hardware design and manufacturing; specialized in high-speed digital circuits, PCB stack-up, EMI/EMC, layout techniques, component selection, etc. EMPLOYMENT HISTORY

2014.11 – 2017.03: Hardware Engineer, Foxconn Technology Group, Tianjin, P.R. China Foxconn CESBG (Cloud Enterprise Solutions Business Group) provides cloud storage & computing solutions. Notable customers include HP, IBM, Nokia, Alibaba, etc. As a HW engineer, I participated in the design, manufacturing and testing of Intel platform servers:

U.2/SAS/SATA HDD backplanes. Schematics design and inspection (component selection, termination, bypass/de-coupling, pull up/down, CPLD, LED indicators, power budget, VR/PDN, etc.).

PCB stack-up design and impedance control. Draft layout guideline and .brd file inspection; netlist compare; de-rating; footprints check, etc. Write Gerber release documents and fab notes.

Low speed signals testing (bring up, power stress, clock, SMBus, etc.). Write test plans and reports.

Review and respond customers’ feedback. Co-work with other teams on EVT, DVT, (PVT) and MP.

(Cost, lead-time, halogen free/RoHS compliant, DFx, EMC, mechanical, thermal issues, etc.). 2011.02 – 2014.07: Quality Control Inspector, IMS (Innovative Manufacturing Source), Calgary, AB, CA

Inspect and test the incoming components, hardware and bare PCBs; perform inspection (SMT, through-hole and cable soldering) on all assemblies; ensure all products meet IPC standards and customers' requirements; identify any quality issues and work with production teams to resolve them.

Ensure all WOs are completed and comply with individual assembly specifications and company standards; ensure all WOs are completed on time, prior to customer requested ship dates.

Write non-conformance reports and investigate the causes. Contribute to the maintenance and compliance of company SOP/Quality Management Systems.

EDUCATION

2008.09 – 2010.10: MSEE, Department of Electrical & Computer Engineering, University of Saskatchewan

Research on radiation effects. Radiation tolerant integrated circuits design for space applications.

Schematic and layout design under TSMC 0.18um, 0.13um and STM 90nm CMOS processes; DRC/LVS, parasitic extraction, post-layout simulation and tape out. Design the test board, build test bench and test under radioactive environments emulated by laser beams. Technical writing. (joint project with NASA) 2003.09 – 2007.07: B.Eng., School of Electronic and Information Engineering, Tianjin University, P.R. China

Microelectronics and Solid State Electronics