Design Engineer

AVANTIKA PAL

Email id: **************@*****.***

Contact number: +91-995*******

OBJECTIVE

Seeking an opportunity to be an integral part of a highly professional and dynamic organization which demands best of my technical and analytical skills for the benefit of the organization, providing me an environment to learn and excel.

PROFESSIONAL WORK EXPERIENCE

• 1 year Training experience as PHYSICAL design engineer.

ACADEMIC QUALIFICATION

•B.Tech (2012-15) in Electronics and Communication Engineering, Inderprastha Engineering college (UPTU) with an aggregate of 69.66%

•Diploma: 72.26%, Govt. girls polytechnic lucknow (BTE) 2011

•10th: 54%, Govt. girls inter college ghazipur (U.P) 2008

PROFESSIONAL TRAINING

•PHYSICAL LAYOUT Design from Pine Training Academy, Ghaziabad, from July, 2014 to july 2015.

•ASIC Design Flow in Frontend and Backend.

•FPGA Logic System Design.

•Advance Workshop in Layout Design using Cadence – Virtuoso from ENTUPLE Technologies at IPEC

TECHNICAL COMPETENCIES

Languages Known -

•Hardware Design:Verilog

•Tools Used Design: Cadence-Virtuoso (VSEL, LayoutXL), Silvaco (Gateway, Expert), Symica.

•Simulator: Cadence-Spectre, ADEL, Silvaco-ISIM, Smart Spice.

•Verification: Cadence-Assura, Silvaco-Guardian

Synthesis: Xilinx ISE

Other Tools - OrCAD (PSpice, CaptureCIS), MATLAB,FHSS.

•Technical Subjects - Digital electronics, Analog CMOS Integration Circuit

TECHNICAL PROJECTS

1.Title : Two stage operational Amplifier gpdk180

•Tool Used:

Design – VSEL, Simulator – ADEL, VIVA, Layout – LayoutXL, Verification – Assura.

•Details: Study and Design of the two stage op-amp schematic with proper analysis and simulation at all corners with the desire specification gain, slew rate, bandwidth, PM and compensation techniques (miller compensation, nulling resistance compensation), ICMR at supply and temperature.

Floor planning of Layout design to optimize area.

Symmetrical routing of both input lines.

Common centroid layout for input differential pair and all possible current mirrors

•Level Shifter

Team Size: 3 Place: Pine Training Academy Tool: Virtuoso

Description: Layout design of level shifter at gpdk180nm, cleaned DRC and LVS, considered electromigration (at 125C), and latch up.

•Inverter (7 track)/NAND/NOR

Place: Pine Training Academy Tool: Silvaco (Expert and Gateway)

Description: Layout design and schematic, Physical verification of the design, applying the concept of folding, fingering and sharing for a pmos w/l 10u/2u and for nmos 6u/2u.

•FIFO design

Place: Pine Training Academy

Description: Using Xilinx tool, designed an 8 bit wide 16 words deep synthesizable asynchronous FIFO with 2-D vector array to store words using Verilog HDL.

•Design of SierpinaskiRhombicFractalPatch Antenna ForMultibandApplications

Team size: 4 Place: Inderprastha Engineering College Tool: FHSS 13.0

Description: Antenna design at Operating Frequency (f)2.45GHz,Substrate (FR4) .And also done simulation by analysis of first,second and third iteration.

AWARDS/CERTIFICATES

•Organized- Technical Organizer in Advance workshop of Layout Design using Cadence Virtuoso

•Technical Organizer in a Gentronix club at IPEC, Ghaziabad.

• Advance workshop on asic layout design with virtuoso cadence tool

•Participate in National seminar on recent trends in microelectronics and communication systems-2015

•Won first prize in 800m race &javeline throw at Zonal level.

•Participate at state level(javeline,disc throw,800m race).

•Won first prize in 800m race, Javeline throw, Disc throw at college level.

•Winner of Cricket in sports fest at college.

• Won first prize in FRILLZ in college fest.

PERSONAL INFORMATION

Date of birth: 11 July, 1995

Father Name: Kailash prakash

Address: D/45 Gora bazaar ghazipur (U.P)

DECLARATION

I hereby declare that all the information are true and correct to the best of my knowledge and belief.

Date: Signature:

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